[PATCH 06/16] eal: fix out of bounds access in devargs

[PATCH 06/16] eal: fix out of bounds access in devargs

[Stephen Hemminger]

The code for parsing layers in devargs could reference past
the end of layers[] array on stack.

Link: https://pvs-studio.com/en/blog/posts/cpp/1183/

Fixes: 9a1a9e4a2ddd ("devargs: support path value with global device syntax")
Cc: xuemingl@nvidia.com
Cc: stable@dpdk.org
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
---
 lib/eal/common/eal_common_devargs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/eal/common/eal_common_devargs.c b/lib/eal/common/eal_common_devargs.c
index a64805b268..dd857fc839 100644
--- a/lib/eal/common/eal_common_devargs.c
+++ b/lib/eal/common/eal_common_devargs.c
@@ -88,7 +88,7 @@ rte_devargs_layers_parse(struct rte_devargs *devargs,
 	s = devargs->data;
 
 	while (s != NULL) {
-		if (nblayer > RTE_DIM(layers)) {
+		if (nblayer >= RTE_DIM(layers)) {
 			ret = -E2BIG;
 			goto get_out;
 		}
-- 
2.45.2

[PATCH 07/16] net/qede: fix missing debug string

[Stephen Hemminger]

The array of debug status strings did not match possible enum
values. Add the missing element and a static assert to make sure
the table has all possible values.

For more complete description see.
Link: https://pvs-studio.com/en/blog/posts/cpp/1176/

Fixes: ec55c118792b ("net/qede: add infrastructure for debug data collection")
Cc: rmody@marvell.com
Cc: stable@dpdk.org

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
---
 drivers/net/qede/qede_debug.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/net/qede/qede_debug.c b/drivers/net/qede/qede_debug.c
index 18f2d988fb..4997f98a5d 100644
--- a/drivers/net/qede/qede_debug.c
+++ b/drivers/net/qede/qede_debug.c
@@ -5614,6 +5614,8 @@ static const char * const s_status_str[] = {
 	/* DBG_STATUS_INVALID_FILTER_TRIGGER_DWORDS */
 	"The filter/trigger constraint dword offsets are not enabled for recording",
 
+	/* DBG_STATUS_NO_MATCHING_FRAMING_MODE */
+	"No matching frame mode",
 
 	/* DBG_STATUS_VFC_READ_ERROR */
 	"Error reading from VFC",
@@ -5759,6 +5761,7 @@ static const char * const s_status_str[] = {
 	/* DBG_STATUS_MISSING_TRIGGER_STATE_STORM */
 	"When triggering on Storm data, the Storm to trigger on must be specified"
 };
+static_assert(MAX_DBG_STATUS == RTE_DIM(s_status_str), "status string table mismatch");
 
 /* Idle check severity names array */
 static const char * const s_idle_chk_severity_str[] = {
-- 
2.45.2

[PATCH 09/16] examples/ptpclient: fix self memcmp

[Stephen Hemminger]

Calling memcmp on same structure will always be true.
Replace with same conditional used elsewhere.

Link: https://pvs-studio.com/en/blog/posts/cpp/1183/

Fixes: ab129e9065a5 ("examples/ptpclient: add minimal PTP client")
Cc: danielx.t.mrzyglod@intel.com
Cc: stable@dpdk.org

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
---
 examples/ptpclient/ptpclient.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/examples/ptpclient/ptpclient.c b/examples/ptpclient/ptpclient.c
index 2ec532d058..d6dff2eb7e 100644
--- a/examples/ptpclient/ptpclient.c
+++ b/examples/ptpclient/ptpclient.c
@@ -419,7 +419,7 @@ parse_sync(struct ptpv2_time_receiver_ordinary *ptp_data, uint16_t rx_tstamp_idx
 		ptp_data->ptpset = 1;
 	}
 
-	if (memcmp(&ptp_hdr->source_port_id.clock_id,
+	if (memcmp(&ptp_data->transmitter_clock_id,
 			&ptp_hdr->source_port_id.clock_id,
 			sizeof(struct clock_id)) == 0) {
 
-- 
2.45.2

[PATCH 11/16] net/hinic: fix flow type bitmask overflow

[Stephen Hemminger]

The type mask is 64 bit value, doing a shift of literal 1 (32 bit)
will result in int type (32 bit) and cause truncation.

Link: https://pvs-studio.com/en/blog/posts/cpp/1183/
Fixes: f4ca3fd54c4d ("net/hinic: create and destroy flow director filter")
Cc: cloud.wangxiaoyun@huawei.com
Cc: stable@dpdk.org

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
---
 drivers/net/hinic/hinic_pmd_flow.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/net/hinic/hinic_pmd_flow.c b/drivers/net/hinic/hinic_pmd_flow.c
index 8fdd5a35be..6b1ca6ff88 100644
--- a/drivers/net/hinic/hinic_pmd_flow.c
+++ b/drivers/net/hinic/hinic_pmd_flow.c
@@ -1979,8 +1979,8 @@ static int hinic_lookup_new_filter(struct hinic_5tuple_filter *filter,
 		return -EINVAL;
 	}
 
-	if (!(filter_info->type_mask & (1 << type_id))) {
-		filter_info->type_mask |= 1 << type_id;
+	if (!(filter_info->type_mask & (UINT64_C(1) << type_id))) {
+		filter_info->type_mask |= UINT64_C(1) << type_id;
 		filter->index = type_id;
 		filter_info->pkt_filters[type_id].enable = true;
 		filter_info->pkt_filters[type_id].pkt_proto =
@@ -2138,7 +2138,7 @@ static void hinic_remove_5tuple_filter(struct rte_eth_dev *dev,
 	filter_info->pkt_type = 0;
 	filter_info->qid = 0;
 	filter_info->pkt_filters[filter->index].qid = 0;
-	filter_info->type_mask &= ~(1 <<  (filter->index));
+	filter_info->type_mask &= ~(UINT64_C(1) << filter->index);
 	TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
 
 	rte_free(filter);
@@ -2268,8 +2268,8 @@ hinic_ethertype_filter_insert(struct hinic_filter_info *filter_info,
 	if (id < 0)
 		return -EINVAL;
 
-	if (!(filter_info->type_mask & (1 << id))) {
-		filter_info->type_mask |= 1 << id;
+	if (!(filter_info->type_mask & (UINT64_C(1) << id))) {
+		filter_info->type_mask |= UINT64_C(1) << id;
 		filter_info->pkt_filters[id].pkt_proto =
 			ethertype_filter->pkt_proto;
 		filter_info->pkt_filters[id].enable = ethertype_filter->enable;
@@ -2289,7 +2289,7 @@ hinic_ethertype_filter_remove(struct hinic_filter_info *filter_info,
 		return;
 
 	filter_info->pkt_type = 0;
-	filter_info->type_mask &= ~(1 << idx);
+	filter_info->type_mask &= ~(UINT64_C(1) << idx);
 	filter_info->pkt_filters[idx].pkt_proto = (uint16_t)0;
 	filter_info->pkt_filters[idx].enable = FALSE;
 	filter_info->pkt_filters[idx].qid = 0;
@@ -2355,7 +2355,7 @@ hinic_add_del_ethertype_filter(struct rte_eth_dev *dev,
 		if (i < 0)
 			return -EINVAL;
 
-		if ((filter_info->type_mask & (1 << i))) {
+		if ((filter_info->type_mask & (UINT64_C(1) << i))) {
 			filter_info->pkt_filters[i].enable = FALSE;
 			(void)hinic_set_fdir_filter(nic_dev->hwdev,
 					filter_info->pkt_type,
-- 
2.45.2

[PATCH 12/16] crypto/dpaa2_sec: fix bitmask truncation

[Stephen Hemminger]

The dqrr_held mask is 64 bit but updates were getting truncated
because 1 is of type int (32 bit) and the result shift of int is of
type int (32 bit); therefore any value >= 32 would get truncated.

Link: https://pvs-studio.com/en/blog/posts/cpp/1183/

Fixes: a77db24643b7 ("crypto/dpaa2_sec: support atomic queues")
Cc: ashish.jain@nxp.com
Cc: stable@dpdk.org

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
---
 drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
index ec6577f64c..7ad8fd47dd 100644
--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
@@ -1491,8 +1491,8 @@ dpaa2_sec_enqueue_burst(void *qp, struct rte_crypto_op **ops,
 			if (*dpaa2_seqn((*ops)->sym->m_src)) {
 				if (*dpaa2_seqn((*ops)->sym->m_src) & QBMAN_ENQUEUE_FLAG_DCA) {
 					DPAA2_PER_LCORE_DQRR_SIZE--;
-					DPAA2_PER_LCORE_DQRR_HELD &= ~(1 <<
-					*dpaa2_seqn((*ops)->sym->m_src) &
+					DPAA2_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) <<
+						*dpaa2_seqn((*ops)->sym->m_src) &
 					QBMAN_EQCR_DCA_IDXMASK);
 				}
 				flags[loop] = *dpaa2_seqn((*ops)->sym->m_src);
@@ -1772,7 +1772,7 @@ dpaa2_sec_set_enqueue_descriptor(struct dpaa2_queue *dpaa2_q,
 		dq_idx = *dpaa2_seqn(m) - 1;
 		qbman_eq_desc_set_dca(eqdesc, 1, dq_idx, 0);
 		DPAA2_PER_LCORE_DQRR_SIZE--;
-		DPAA2_PER_LCORE_DQRR_HELD &= ~(1 << dq_idx);
+		DPAA2_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) << dq_idx);
 	}
 	*dpaa2_seqn(m) = DPAA2_INVALID_MBUF_SEQN;
 }
@@ -4055,7 +4055,7 @@ dpaa2_sec_process_atomic_event(struct qbman_swp *swp __rte_unused,
 	dqrr_index = qbman_get_dqrr_idx(dq);
 	*dpaa2_seqn(crypto_op->sym->m_src) = QBMAN_ENQUEUE_FLAG_DCA | dqrr_index;
 	DPAA2_PER_LCORE_DQRR_SIZE++;
-	DPAA2_PER_LCORE_DQRR_HELD |= 1 << dqrr_index;
+	DPAA2_PER_LCORE_DQRR_HELD |= UINT64_C(1) << dqrr_index;
 	DPAA2_PER_LCORE_DQRR_MBUF(dqrr_index) = crypto_op->sym->m_src;
 	ev->event_ptr = crypto_op;
 }
-- 
2.45.2

Re: [PATCH 12/16] crypto/dpaa2_sec: fix bitmask truncation

[Hemant Agrawal]

On 15-11-2024 11:35, Stephen Hemminger wrote:
> The dqrr_held mask is 64 bit but updates were getting truncated
> because 1 is of type int (32 bit) and the result shift of int is of
> type int (32 bit); therefore any value >= 32 would get truncated.
>
> Link: https://pvs-studio.com/en/blog/posts/cpp/1183/
>
> Fixes: a77db24643b7 ("crypto/dpaa2_sec: support atomic queues")
> Cc: ashish.jain@nxp.com
> Cc: stable@dpdk.org
>
> Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
> ---
>   drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 8 ++++----
>   1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
> index ec6577f64c..7ad8fd47dd 100644
> --- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
> +++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
> @@ -1491,8 +1491,8 @@ dpaa2_sec_enqueue_burst(void *qp, struct rte_crypto_op **ops,
>   			if (*dpaa2_seqn((*ops)->sym->m_src)) {
>   				if (*dpaa2_seqn((*ops)->sym->m_src) & QBMAN_ENQUEUE_FLAG_DCA) {
>   					DPAA2_PER_LCORE_DQRR_SIZE--;
> -					DPAA2_PER_LCORE_DQRR_HELD &= ~(1 <<
> -					*dpaa2_seqn((*ops)->sym->m_src) &
> +					DPAA2_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) <<
> +						*dpaa2_seqn((*ops)->sym->m_src) &
>   					QBMAN_EQCR_DCA_IDXMASK);
>   				}
>   				flags[loop] = *dpaa2_seqn((*ops)->sym->m_src);
> @@ -1772,7 +1772,7 @@ dpaa2_sec_set_enqueue_descriptor(struct dpaa2_queue *dpaa2_q,
>   		dq_idx = *dpaa2_seqn(m) - 1;
>   		qbman_eq_desc_set_dca(eqdesc, 1, dq_idx, 0);
>   		DPAA2_PER_LCORE_DQRR_SIZE--;
> -		DPAA2_PER_LCORE_DQRR_HELD &= ~(1 << dq_idx);
> +		DPAA2_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) << dq_idx);
>   	}
>   	*dpaa2_seqn(m) = DPAA2_INVALID_MBUF_SEQN;
>   }
> @@ -4055,7 +4055,7 @@ dpaa2_sec_process_atomic_event(struct qbman_swp *swp __rte_unused,
>   	dqrr_index = qbman_get_dqrr_idx(dq);
>   	*dpaa2_seqn(crypto_op->sym->m_src) = QBMAN_ENQUEUE_FLAG_DCA | dqrr_index;
>   	DPAA2_PER_LCORE_DQRR_SIZE++;
> -	DPAA2_PER_LCORE_DQRR_HELD |= 1 << dqrr_index;
> +	DPAA2_PER_LCORE_DQRR_HELD |= UINT64_C(1) << dqrr_index;
>   	DPAA2_PER_LCORE_DQRR_MBUF(dqrr_index) = crypto_op->sym->m_src;
>   	ev->event_ptr = crypto_op;
>   }
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>

[PATCH 13/16] crypto/dpaa_sec: fix bitmask truncation

[Stephen Hemminger]

The dqrr_held mask is 64 bit but updates were getting truncated
because 1 is of type int (32 bit) and the result shift of int is of
type int (32 bit); therefore any value >= 32 would get truncated.

Link: https://pvs-studio.com/en/blog/posts/cpp/1183/

Fixes: fe3688ba7950 ("crypto/dpaa_sec: support event crypto adapter")
Cc: akhil.goyal@nxp.com
Cc: stable@dpdk.org

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
---
 drivers/crypto/dpaa_sec/dpaa_sec.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/crypto/dpaa_sec/dpaa_sec.c b/drivers/crypto/dpaa_sec/dpaa_sec.c
index 3fa88ca968..e117cd77a6 100644
--- a/drivers/crypto/dpaa_sec/dpaa_sec.c
+++ b/drivers/crypto/dpaa_sec/dpaa_sec.c
@@ -1907,13 +1907,12 @@ dpaa_sec_enqueue_burst(void *qp, struct rte_crypto_op **ops,
 			op = *(ops++);
 			if (*dpaa_seqn(op->sym->m_src) != 0) {
 				index = *dpaa_seqn(op->sym->m_src) - 1;
-				if (DPAA_PER_LCORE_DQRR_HELD & (1 << index)) {
+				if (DPAA_PER_LCORE_DQRR_HELD & (UINT64_C(1) << index)) {
 					/* QM_EQCR_DCA_IDXMASK = 0x0f */
 					flags[loop] = ((index & 0x0f) << 8);
 					flags[loop] |= QMAN_ENQUEUE_FLAG_DCA;
 					DPAA_PER_LCORE_DQRR_SIZE--;
-					DPAA_PER_LCORE_DQRR_HELD &=
-								~(1 << index);
+					DPAA_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) << index);
 				}
 			}
 
@@ -3500,7 +3499,7 @@ dpaa_sec_process_atomic_event(void *event,
 	/* Save active dqrr entries */
 	index = ((uintptr_t)dqrr >> 6) & (16/*QM_DQRR_SIZE*/ - 1);
 	DPAA_PER_LCORE_DQRR_SIZE++;
-	DPAA_PER_LCORE_DQRR_HELD |= 1 << index;
+	DPAA_PER_LCORE_DQRR_HELD |= UINT64_C(1) << index;
 	DPAA_PER_LCORE_DQRR_MBUF(index) = ctx->op->sym->m_src;
 	ev->impl_opaque = index + 1;
 	*dpaa_seqn(ctx->op->sym->m_src) = (uint32_t)index + 1;
-- 
2.45.2

Re: [PATCH 13/16] crypto/dpaa_sec: fix bitmask truncation

[Hemant Agrawal]

On 15-11-2024 11:35, Stephen Hemminger wrote:
> The dqrr_held mask is 64 bit but updates were getting truncated
> because 1 is of type int (32 bit) and the result shift of int is of
> type int (32 bit); therefore any value >= 32 would get truncated.
>
> Link: https://pvs-studio.com/en/blog/posts/cpp/1183/
>
> Fixes: fe3688ba7950 ("crypto/dpaa_sec: support event crypto adapter")
> Cc: akhil.goyal@nxp.com
> Cc: stable@dpdk.org
>
> Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
> ---
>   drivers/crypto/dpaa_sec/dpaa_sec.c | 7 +++----
>   1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/crypto/dpaa_sec/dpaa_sec.c b/drivers/crypto/dpaa_sec/dpaa_sec.c
> index 3fa88ca968..e117cd77a6 100644
> --- a/drivers/crypto/dpaa_sec/dpaa_sec.c
> +++ b/drivers/crypto/dpaa_sec/dpaa_sec.c
> @@ -1907,13 +1907,12 @@ dpaa_sec_enqueue_burst(void *qp, struct rte_crypto_op **ops,
>   			op = *(ops++);
>   			if (*dpaa_seqn(op->sym->m_src) != 0) {
>   				index = *dpaa_seqn(op->sym->m_src) - 1;
> -				if (DPAA_PER_LCORE_DQRR_HELD & (1 << index)) {
> +				if (DPAA_PER_LCORE_DQRR_HELD & (UINT64_C(1) << index)) {
>   					/* QM_EQCR_DCA_IDXMASK = 0x0f */
>   					flags[loop] = ((index & 0x0f) << 8);
>   					flags[loop] |= QMAN_ENQUEUE_FLAG_DCA;
>   					DPAA_PER_LCORE_DQRR_SIZE--;
> -					DPAA_PER_LCORE_DQRR_HELD &=
> -								~(1 << index);
> +					DPAA_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) << index);
>   				}
>   			}
>   
> @@ -3500,7 +3499,7 @@ dpaa_sec_process_atomic_event(void *event,
>   	/* Save active dqrr entries */
>   	index = ((uintptr_t)dqrr >> 6) & (16/*QM_DQRR_SIZE*/ - 1);
>   	DPAA_PER_LCORE_DQRR_SIZE++;
> -	DPAA_PER_LCORE_DQRR_HELD |= 1 << index;
> +	DPAA_PER_LCORE_DQRR_HELD |= UINT64_C(1) << index;
>   	DPAA_PER_LCORE_DQRR_MBUF(index) = ctx->op->sym->m_src;
>   	ev->impl_opaque = index + 1;
>   	*dpaa_seqn(ctx->op->sym->m_src) = (uint32_t)index + 1;
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>

[PATCH 14/16] event/dpaa: fix bitmask truncation

[Stephen Hemminger]

More bitmask truncation from mask computation.

Fixes: 0ee17f79ebd0 ("event/dpaa: add enqueue/dequeue")
Cc: sunil.kori@nxp.com
Cc: stable@dpdk.org

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
---
 drivers/event/dpaa/dpaa_eventdev.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/event/dpaa/dpaa_eventdev.c b/drivers/event/dpaa/dpaa_eventdev.c
index 853cc1ecf9..400e0ecd1c 100644
--- a/drivers/event/dpaa/dpaa_eventdev.c
+++ b/drivers/event/dpaa/dpaa_eventdev.c
@@ -102,7 +102,7 @@ dpaa_event_enqueue_burst(void *port, const struct rte_event ev[],
 			qman_dca_index(ev[i].impl_opaque, 0);
 			mbuf = DPAA_PER_LCORE_DQRR_MBUF(i);
 			*dpaa_seqn(mbuf) = DPAA_INVALID_MBUF_SEQN;
-			DPAA_PER_LCORE_DQRR_HELD &= ~(1 << i);
+			DPAA_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) << i);
 			DPAA_PER_LCORE_DQRR_SIZE--;
 			break;
 		default:
@@ -199,11 +199,11 @@ dpaa_event_dequeue_burst(void *port, struct rte_event ev[],
 	/* Check if there are atomic contexts to be released */
 	i = 0;
 	while (DPAA_PER_LCORE_DQRR_SIZE) {
-		if (DPAA_PER_LCORE_DQRR_HELD & (1 << i)) {
+		if (DPAA_PER_LCORE_DQRR_HELD & (UINT64_C(1) << i)) {
 			qman_dca_index(i, 0);
 			mbuf = DPAA_PER_LCORE_DQRR_MBUF(i);
 			*dpaa_seqn(mbuf) = DPAA_INVALID_MBUF_SEQN;
-			DPAA_PER_LCORE_DQRR_HELD &= ~(1 << i);
+			DPAA_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) << i);
 			DPAA_PER_LCORE_DQRR_SIZE--;
 		}
 		i++;
@@ -263,11 +263,11 @@ dpaa_event_dequeue_burst_intr(void *port, struct rte_event ev[],
 	/* Check if there are atomic contexts to be released */
 	i = 0;
 	while (DPAA_PER_LCORE_DQRR_SIZE) {
-		if (DPAA_PER_LCORE_DQRR_HELD & (1 << i)) {
+		if (DPAA_PER_LCORE_DQRR_HELD & (UINT64_C(1) << i)) {
 			qman_dca_index(i, 0);
 			mbuf = DPAA_PER_LCORE_DQRR_MBUF(i);
 			*dpaa_seqn(mbuf) = DPAA_INVALID_MBUF_SEQN;
-			DPAA_PER_LCORE_DQRR_HELD &= ~(1 << i);
+			DPAA_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) << i);
 			DPAA_PER_LCORE_DQRR_SIZE--;
 		}
 		i++;
-- 
2.45.2

Re: [PATCH 14/16] event/dpaa: fix bitmask truncation

[Hemant Agrawal]

On 15-11-2024 11:35, Stephen Hemminger wrote:
> More bitmask truncation from mask computation.
>
> Fixes: 0ee17f79ebd0 ("event/dpaa: add enqueue/dequeue")
> Cc: sunil.kori@nxp.com
> Cc: stable@dpdk.org
>
> Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
> ---
>   drivers/event/dpaa/dpaa_eventdev.c | 10 +++++-----
>   1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/event/dpaa/dpaa_eventdev.c b/drivers/event/dpaa/dpaa_eventdev.c
> index 853cc1ecf9..400e0ecd1c 100644
> --- a/drivers/event/dpaa/dpaa_eventdev.c
> +++ b/drivers/event/dpaa/dpaa_eventdev.c
> @@ -102,7 +102,7 @@ dpaa_event_enqueue_burst(void *port, const struct rte_event ev[],
>   			qman_dca_index(ev[i].impl_opaque, 0);
>   			mbuf = DPAA_PER_LCORE_DQRR_MBUF(i);
>   			*dpaa_seqn(mbuf) = DPAA_INVALID_MBUF_SEQN;
> -			DPAA_PER_LCORE_DQRR_HELD &= ~(1 << i);
> +			DPAA_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) << i);
>   			DPAA_PER_LCORE_DQRR_SIZE--;
>   			break;
>   		default:
> @@ -199,11 +199,11 @@ dpaa_event_dequeue_burst(void *port, struct rte_event ev[],
>   	/* Check if there are atomic contexts to be released */
>   	i = 0;
>   	while (DPAA_PER_LCORE_DQRR_SIZE) {
> -		if (DPAA_PER_LCORE_DQRR_HELD & (1 << i)) {
> +		if (DPAA_PER_LCORE_DQRR_HELD & (UINT64_C(1) << i)) {
>   			qman_dca_index(i, 0);
>   			mbuf = DPAA_PER_LCORE_DQRR_MBUF(i);
>   			*dpaa_seqn(mbuf) = DPAA_INVALID_MBUF_SEQN;
> -			DPAA_PER_LCORE_DQRR_HELD &= ~(1 << i);
> +			DPAA_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) << i);
>   			DPAA_PER_LCORE_DQRR_SIZE--;
>   		}
>   		i++;
> @@ -263,11 +263,11 @@ dpaa_event_dequeue_burst_intr(void *port, struct rte_event ev[],
>   	/* Check if there are atomic contexts to be released */
>   	i = 0;
>   	while (DPAA_PER_LCORE_DQRR_SIZE) {
> -		if (DPAA_PER_LCORE_DQRR_HELD & (1 << i)) {
> +		if (DPAA_PER_LCORE_DQRR_HELD & (UINT64_C(1) << i)) {
>   			qman_dca_index(i, 0);
>   			mbuf = DPAA_PER_LCORE_DQRR_MBUF(i);
>   			*dpaa_seqn(mbuf) = DPAA_INVALID_MBUF_SEQN;
> -			DPAA_PER_LCORE_DQRR_HELD &= ~(1 << i);
> +			DPAA_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) << i);
>   			DPAA_PER_LCORE_DQRR_SIZE--;
>   		}
>   		i++;
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>

[PATCH 15/16] net/dpaa: fix bitmask truncation

[Stephen Hemminger]

The dqrr_held mask is 64 bit but updates were getting truncated
because 1 is of type int (32 bit) and the result shift of int is of
type int (32 bit); therefore any value >= 32 would get truncated.

Link: https://pvs-studio.com/en/blog/posts/cpp/1183/

Fixes: 5e7455931442 ("net/dpaa: support Rx queue configurations with eventdev")
Cc: sunil.kori@nxp.com
Cc: stable@dpdk.org

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
---
 drivers/net/dpaa/dpaa_rxtx.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/net/dpaa/dpaa_rxtx.c b/drivers/net/dpaa/dpaa_rxtx.c
index 247e7b92ba..05bd73becf 100644
--- a/drivers/net/dpaa/dpaa_rxtx.c
+++ b/drivers/net/dpaa/dpaa_rxtx.c
@@ -842,7 +842,7 @@ dpaa_rx_cb_atomic(void *event,
 	/* Save active dqrr entries */
 	index = DQRR_PTR2IDX(dqrr);
 	DPAA_PER_LCORE_DQRR_SIZE++;
-	DPAA_PER_LCORE_DQRR_HELD |= 1 << index;
+	DPAA_PER_LCORE_DQRR_HELD |= UINT64_C(1) << index;
 	DPAA_PER_LCORE_DQRR_MBUF(index) = mbuf;
 	ev->impl_opaque = index + 1;
 	*dpaa_seqn(mbuf) = (uint32_t)index + 1;
@@ -1338,13 +1338,12 @@ dpaa_eth_queue_tx(void *q, struct rte_mbuf **bufs, uint16_t nb_bufs)
 			seqn = *dpaa_seqn(mbuf);
 			if (seqn != DPAA_INVALID_MBUF_SEQN) {
 				index = seqn - 1;
-				if (DPAA_PER_LCORE_DQRR_HELD & (1 << index)) {
+				if (DPAA_PER_LCORE_DQRR_HELD & (UINT64_C(1) << index)) {
 					flags[loop] =
 					   ((index & QM_EQCR_DCA_IDXMASK) << 8);
 					flags[loop] |= QMAN_ENQUEUE_FLAG_DCA;
 					DPAA_PER_LCORE_DQRR_SIZE--;
-					DPAA_PER_LCORE_DQRR_HELD &=
-								~(1 << index);
+					DPAA_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) << index);
 				}
 			}
 
-- 
2.45.2

Re: [PATCH 15/16] net/dpaa: fix bitmask truncation

[Hemant Agrawal]

Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>

On 15-11-2024 11:35, Stephen Hemminger wrote:
> The dqrr_held mask is 64 bit but updates were getting truncated
> because 1 is of type int (32 bit) and the result shift of int is of
> type int (32 bit); therefore any value >= 32 would get truncated.
>
> Link: https://pvs-studio.com/en/blog/posts/cpp/1183/
>
> Fixes: 5e7455931442 ("net/dpaa: support Rx queue configurations with eventdev")
> Cc: sunil.kori@nxp.com
> Cc: stable@dpdk.org
>
> Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
> ---
>   drivers/net/dpaa/dpaa_rxtx.c | 7 +++----
>   1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/net/dpaa/dpaa_rxtx.c b/drivers/net/dpaa/dpaa_rxtx.c
> index 247e7b92ba..05bd73becf 100644
> --- a/drivers/net/dpaa/dpaa_rxtx.c
> +++ b/drivers/net/dpaa/dpaa_rxtx.c
> @@ -842,7 +842,7 @@ dpaa_rx_cb_atomic(void *event,
>   	/* Save active dqrr entries */
>   	index = DQRR_PTR2IDX(dqrr);
>   	DPAA_PER_LCORE_DQRR_SIZE++;
> -	DPAA_PER_LCORE_DQRR_HELD |= 1 << index;
> +	DPAA_PER_LCORE_DQRR_HELD |= UINT64_C(1) << index;
>   	DPAA_PER_LCORE_DQRR_MBUF(index) = mbuf;
>   	ev->impl_opaque = index + 1;
>   	*dpaa_seqn(mbuf) = (uint32_t)index + 1;
> @@ -1338,13 +1338,12 @@ dpaa_eth_queue_tx(void *q, struct rte_mbuf **bufs, uint16_t nb_bufs)
>   			seqn = *dpaa_seqn(mbuf);
>   			if (seqn != DPAA_INVALID_MBUF_SEQN) {
>   				index = seqn - 1;
> -				if (DPAA_PER_LCORE_DQRR_HELD & (1 << index)) {
> +				if (DPAA_PER_LCORE_DQRR_HELD & (UINT64_C(1) << index)) {
>   					flags[loop] =
>   					   ((index & QM_EQCR_DCA_IDXMASK) << 8);
>   					flags[loop] |= QMAN_ENQUEUE_FLAG_DCA;
>   					DPAA_PER_LCORE_DQRR_SIZE--;
> -					DPAA_PER_LCORE_DQRR_HELD &=
> -								~(1 << index);
> +					DPAA_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) << index);
>   				}
>   			}
>   

[PATCH 16/16] net/dpaa2: fix bitmask truncation

[Stephen Hemminger]

The dqrr_held mask is 64 bit but updates were getting truncated
because 1 is of type int (32 bit) and the result shift of int is of
type int (32 bit); therefore any value >= 32 would get truncated.

Link: https://pvs-studio.com/en/blog/posts/cpp/1183/

Fixes: 2d3788631862 ("net/dpaa2: support atomic queues")
Cc: nipun.gupta@nxp.com
Cc: stable@dpdk.org

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
---
 drivers/net/dpaa2/dpaa2_rxtx.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/net/dpaa2/dpaa2_rxtx.c b/drivers/net/dpaa2/dpaa2_rxtx.c
index e3b6c7e460..e253bccecd 100644
--- a/drivers/net/dpaa2/dpaa2_rxtx.c
+++ b/drivers/net/dpaa2/dpaa2_rxtx.c
@@ -933,7 +933,7 @@ dpaa2_dev_process_atomic_event(struct qbman_swp *swp __rte_unused,
 	dqrr_index = qbman_get_dqrr_idx(dq);
 	*dpaa2_seqn(ev->mbuf) = dqrr_index + 1;
 	DPAA2_PER_LCORE_DQRR_SIZE++;
-	DPAA2_PER_LCORE_DQRR_HELD |= 1 << dqrr_index;
+	DPAA2_PER_LCORE_DQRR_HELD |= UINT64_C(1) << dqrr_index;
 	DPAA2_PER_LCORE_DQRR_MBUF(dqrr_index) = ev->mbuf;
 }
 
@@ -1317,7 +1317,7 @@ dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
 				flags[loop] = QBMAN_ENQUEUE_FLAG_DCA |
 						dqrr_index;
 				DPAA2_PER_LCORE_DQRR_SIZE--;
-				DPAA2_PER_LCORE_DQRR_HELD &= ~(1 << dqrr_index);
+				DPAA2_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) << dqrr_index);
 				*dpaa2_seqn(*bufs) = DPAA2_INVALID_MBUF_SEQN;
 			}
 
@@ -1575,7 +1575,7 @@ dpaa2_set_enqueue_descriptor(struct dpaa2_queue *dpaa2_q,
 		dq_idx = *dpaa2_seqn(m) - 1;
 		qbman_eq_desc_set_dca(eqdesc, 1, dq_idx, 0);
 		DPAA2_PER_LCORE_DQRR_SIZE--;
-		DPAA2_PER_LCORE_DQRR_HELD &= ~(1 << dq_idx);
+		DPAA2_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) << dq_idx);
 	}
 	*dpaa2_seqn(m) = DPAA2_INVALID_MBUF_SEQN;
 }
-- 
2.45.2

Re: [PATCH 16/16] net/dpaa2: fix bitmask truncation

[Hemant Agrawal]

Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>

On 15-11-2024 11:35, Stephen Hemminger wrote:
> The dqrr_held mask is 64 bit but updates were getting truncated
> because 1 is of type int (32 bit) and the result shift of int is of
> type int (32 bit); therefore any value >= 32 would get truncated.
>
> Link: https://pvs-studio.com/en/blog/posts/cpp/1183/
>
> Fixes: 2d3788631862 ("net/dpaa2: support atomic queues")
> Cc: nipun.gupta@nxp.com
> Cc: stable@dpdk.org
>
> Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
> ---
>   drivers/net/dpaa2/dpaa2_rxtx.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/net/dpaa2/dpaa2_rxtx.c b/drivers/net/dpaa2/dpaa2_rxtx.c
> index e3b6c7e460..e253bccecd 100644
> --- a/drivers/net/dpaa2/dpaa2_rxtx.c
> +++ b/drivers/net/dpaa2/dpaa2_rxtx.c
> @@ -933,7 +933,7 @@ dpaa2_dev_process_atomic_event(struct qbman_swp *swp __rte_unused,
>   	dqrr_index = qbman_get_dqrr_idx(dq);
>   	*dpaa2_seqn(ev->mbuf) = dqrr_index + 1;
>   	DPAA2_PER_LCORE_DQRR_SIZE++;
> -	DPAA2_PER_LCORE_DQRR_HELD |= 1 << dqrr_index;
> +	DPAA2_PER_LCORE_DQRR_HELD |= UINT64_C(1) << dqrr_index;
>   	DPAA2_PER_LCORE_DQRR_MBUF(dqrr_index) = ev->mbuf;
>   }
>   
> @@ -1317,7 +1317,7 @@ dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
>   				flags[loop] = QBMAN_ENQUEUE_FLAG_DCA |
>   						dqrr_index;
>   				DPAA2_PER_LCORE_DQRR_SIZE--;
> -				DPAA2_PER_LCORE_DQRR_HELD &= ~(1 << dqrr_index);
> +				DPAA2_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) << dqrr_index);
>   				*dpaa2_seqn(*bufs) = DPAA2_INVALID_MBUF_SEQN;
>   			}
>   
> @@ -1575,7 +1575,7 @@ dpaa2_set_enqueue_descriptor(struct dpaa2_queue *dpaa2_q,
>   		dq_idx = *dpaa2_seqn(m) - 1;
>   		qbman_eq_desc_set_dca(eqdesc, 1, dq_idx, 0);
>   		DPAA2_PER_LCORE_DQRR_SIZE--;
> -		DPAA2_PER_LCORE_DQRR_HELD &= ~(1 << dq_idx);
> +		DPAA2_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) << dq_idx);
>   	}
>   	*dpaa2_seqn(m) = DPAA2_INVALID_MBUF_SEQN;
>   }

[PATCH v2 06/19] eal: fix out of bounds access in devargs

[Stephen Hemminger]

The code for parsing layers in devargs could reference past
the end of layers[] array on stack.

Link: https://pvs-studio.com/en/blog/posts/cpp/1183/

Fixes: 9a1a9e4a2ddd ("devargs: support path value with global device syntax")
Cc: xuemingl@nvidia.com
Cc: stable@dpdk.org
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
---
 lib/eal/common/eal_common_devargs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/eal/common/eal_common_devargs.c b/lib/eal/common/eal_common_devargs.c
index a64805b268..dd857fc839 100644
--- a/lib/eal/common/eal_common_devargs.c
+++ b/lib/eal/common/eal_common_devargs.c
@@ -88,7 +88,7 @@ rte_devargs_layers_parse(struct rte_devargs *devargs,
 	s = devargs->data;
 
 	while (s != NULL) {
-		if (nblayer > RTE_DIM(layers)) {
+		if (nblayer >= RTE_DIM(layers)) {
 			ret = -E2BIG;
 			goto get_out;
 		}
-- 
2.45.2

[PATCH v2 07/19] net/qede: fix missing debug string

[Stephen Hemminger]

The array of debug status strings did not match possible enum
values. Add the missing element and a static assert to make sure
the table has all possible values.

For more complete description see.
Link: https://pvs-studio.com/en/blog/posts/cpp/1176/

Fixes: ec55c118792b ("net/qede: add infrastructure for debug data collection")
Cc: rmody@marvell.com
Cc: stable@dpdk.org

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
---
 drivers/net/qede/qede_debug.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/net/qede/qede_debug.c b/drivers/net/qede/qede_debug.c
index 18f2d988fb..1d3147b724 100644
--- a/drivers/net/qede/qede_debug.c
+++ b/drivers/net/qede/qede_debug.c
@@ -4,6 +4,7 @@
  * www.marvell.com
  */
 
+#include <assert.h>
 #include <rte_common.h>
 #include "base/bcm_osal.h"
 #include "base/ecore.h"
@@ -82,6 +83,7 @@ static const char * const s_mem_group_names[] = {
 	"TM_MEM",
 	"TASK_CFC_MEM",
 };
+static_assert(RTE_DIM(s_mem_group_names) == MEM_GROUPS_NUM, "memory group string mismatch");
 
 /* Idle check conditions */
 
@@ -5614,6 +5616,8 @@ static const char * const s_status_str[] = {
 	/* DBG_STATUS_INVALID_FILTER_TRIGGER_DWORDS */
 	"The filter/trigger constraint dword offsets are not enabled for recording",
 
+	/* DBG_STATUS_NO_MATCHING_FRAMING_MODE */
+	"No matching frame mode",
 
 	/* DBG_STATUS_VFC_READ_ERROR */
 	"Error reading from VFC",
@@ -5759,6 +5763,7 @@ static const char * const s_status_str[] = {
 	/* DBG_STATUS_MISSING_TRIGGER_STATE_STORM */
 	"When triggering on Storm data, the Storm to trigger on must be specified"
 };
+static_assert(RTE_DIM(s_status_str) == MAX_DBG_STATUS, "status string table mismatch");
 
 /* Idle check severity names array */
 static const char * const s_idle_chk_severity_str[] = {
-- 
2.45.2

[PATCH v2 09/19] examples/ptpclient: fix self memcmp

[Stephen Hemminger]

Calling memcmp on same structure will always be true.
Replace with same conditional used elsewhere.

Link: https://pvs-studio.com/en/blog/posts/cpp/1183/

Fixes: ab129e9065a5 ("examples/ptpclient: add minimal PTP client")
Cc: danielx.t.mrzyglod@intel.com
Cc: stable@dpdk.org

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
---
 examples/ptpclient/ptpclient.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/examples/ptpclient/ptpclient.c b/examples/ptpclient/ptpclient.c
index 2ec532d058..d6dff2eb7e 100644
--- a/examples/ptpclient/ptpclient.c
+++ b/examples/ptpclient/ptpclient.c
@@ -419,7 +419,7 @@ parse_sync(struct ptpv2_time_receiver_ordinary *ptp_data, uint16_t rx_tstamp_idx
 		ptp_data->ptpset = 1;
 	}
 
-	if (memcmp(&ptp_hdr->source_port_id.clock_id,
+	if (memcmp(&ptp_data->transmitter_clock_id,
 			&ptp_hdr->source_port_id.clock_id,
 			sizeof(struct clock_id)) == 0) {
 
-- 
2.45.2

[PATCH v2 11/19] net/hinic: fix flow type bitmask overflow

[Stephen Hemminger]

The type mask is 64 bit value, doing a shift of literal 1 (32 bit)
will result in int type (32 bit) and cause truncation.

Link: https://pvs-studio.com/en/blog/posts/cpp/1183/
Fixes: f4ca3fd54c4d ("net/hinic: create and destroy flow director filter")
Cc: cloud.wangxiaoyun@huawei.com
Cc: stable@dpdk.org

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
---
 drivers/net/hinic/hinic_pmd_flow.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/net/hinic/hinic_pmd_flow.c b/drivers/net/hinic/hinic_pmd_flow.c
index 8fdd5a35be..6b1ca6ff88 100644
--- a/drivers/net/hinic/hinic_pmd_flow.c
+++ b/drivers/net/hinic/hinic_pmd_flow.c
@@ -1979,8 +1979,8 @@ static int hinic_lookup_new_filter(struct hinic_5tuple_filter *filter,
 		return -EINVAL;
 	}
 
-	if (!(filter_info->type_mask & (1 << type_id))) {
-		filter_info->type_mask |= 1 << type_id;
+	if (!(filter_info->type_mask & (UINT64_C(1) << type_id))) {
+		filter_info->type_mask |= UINT64_C(1) << type_id;
 		filter->index = type_id;
 		filter_info->pkt_filters[type_id].enable = true;
 		filter_info->pkt_filters[type_id].pkt_proto =
@@ -2138,7 +2138,7 @@ static void hinic_remove_5tuple_filter(struct rte_eth_dev *dev,
 	filter_info->pkt_type = 0;
 	filter_info->qid = 0;
 	filter_info->pkt_filters[filter->index].qid = 0;
-	filter_info->type_mask &= ~(1 <<  (filter->index));
+	filter_info->type_mask &= ~(UINT64_C(1) << filter->index);
 	TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
 
 	rte_free(filter);
@@ -2268,8 +2268,8 @@ hinic_ethertype_filter_insert(struct hinic_filter_info *filter_info,
 	if (id < 0)
 		return -EINVAL;
 
-	if (!(filter_info->type_mask & (1 << id))) {
-		filter_info->type_mask |= 1 << id;
+	if (!(filter_info->type_mask & (UINT64_C(1) << id))) {
+		filter_info->type_mask |= UINT64_C(1) << id;
 		filter_info->pkt_filters[id].pkt_proto =
 			ethertype_filter->pkt_proto;
 		filter_info->pkt_filters[id].enable = ethertype_filter->enable;
@@ -2289,7 +2289,7 @@ hinic_ethertype_filter_remove(struct hinic_filter_info *filter_info,
 		return;
 
 	filter_info->pkt_type = 0;
-	filter_info->type_mask &= ~(1 << idx);
+	filter_info->type_mask &= ~(UINT64_C(1) << idx);
 	filter_info->pkt_filters[idx].pkt_proto = (uint16_t)0;
 	filter_info->pkt_filters[idx].enable = FALSE;
 	filter_info->pkt_filters[idx].qid = 0;
@@ -2355,7 +2355,7 @@ hinic_add_del_ethertype_filter(struct rte_eth_dev *dev,
 		if (i < 0)
 			return -EINVAL;
 
-		if ((filter_info->type_mask & (1 << i))) {
+		if ((filter_info->type_mask & (UINT64_C(1) << i))) {
 			filter_info->pkt_filters[i].enable = FALSE;
 			(void)hinic_set_fdir_filter(nic_dev->hwdev,
 					filter_info->pkt_type,
-- 
2.45.2

[PATCH v2 12/19] crypto/dpaa2_sec: fix bitmask truncation

[Stephen Hemminger]

The dqrr_held mask is 64 bit but updates were getting truncated
because 1 is of type int (32 bit) and the result shift of int is of
type int (32 bit); therefore any value >= 32 would get truncated.

Link: https://pvs-studio.com/en/blog/posts/cpp/1183/

Fixes: a77db24643b7 ("crypto/dpaa2_sec: support atomic queues")
Cc: ashish.jain@nxp.com
Cc: stable@dpdk.org

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
 drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
index ec6577f64c..7ad8fd47dd 100644
--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
@@ -1491,8 +1491,8 @@ dpaa2_sec_enqueue_burst(void *qp, struct rte_crypto_op **ops,
 			if (*dpaa2_seqn((*ops)->sym->m_src)) {
 				if (*dpaa2_seqn((*ops)->sym->m_src) & QBMAN_ENQUEUE_FLAG_DCA) {
 					DPAA2_PER_LCORE_DQRR_SIZE--;
-					DPAA2_PER_LCORE_DQRR_HELD &= ~(1 <<
-					*dpaa2_seqn((*ops)->sym->m_src) &
+					DPAA2_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) <<
+						*dpaa2_seqn((*ops)->sym->m_src) &
 					QBMAN_EQCR_DCA_IDXMASK);
 				}
 				flags[loop] = *dpaa2_seqn((*ops)->sym->m_src);
@@ -1772,7 +1772,7 @@ dpaa2_sec_set_enqueue_descriptor(struct dpaa2_queue *dpaa2_q,
 		dq_idx = *dpaa2_seqn(m) - 1;
 		qbman_eq_desc_set_dca(eqdesc, 1, dq_idx, 0);
 		DPAA2_PER_LCORE_DQRR_SIZE--;
-		DPAA2_PER_LCORE_DQRR_HELD &= ~(1 << dq_idx);
+		DPAA2_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) << dq_idx);
 	}
 	*dpaa2_seqn(m) = DPAA2_INVALID_MBUF_SEQN;
 }
@@ -4055,7 +4055,7 @@ dpaa2_sec_process_atomic_event(struct qbman_swp *swp __rte_unused,
 	dqrr_index = qbman_get_dqrr_idx(dq);
 	*dpaa2_seqn(crypto_op->sym->m_src) = QBMAN_ENQUEUE_FLAG_DCA | dqrr_index;
 	DPAA2_PER_LCORE_DQRR_SIZE++;
-	DPAA2_PER_LCORE_DQRR_HELD |= 1 << dqrr_index;
+	DPAA2_PER_LCORE_DQRR_HELD |= UINT64_C(1) << dqrr_index;
 	DPAA2_PER_LCORE_DQRR_MBUF(dqrr_index) = crypto_op->sym->m_src;
 	ev->event_ptr = crypto_op;
 }
-- 
2.45.2

[PATCH v2 13/19] crypto/dpaa_sec: fix bitmask truncation

[Stephen Hemminger]

The dqrr_held mask is 64 bit but updates were getting truncated
because 1 is of type int (32 bit) and the result shift of int is of
type int (32 bit); therefore any value >= 32 would get truncated.

Link: https://pvs-studio.com/en/blog/posts/cpp/1183/

Fixes: fe3688ba7950 ("crypto/dpaa_sec: support event crypto adapter")
Cc: akhil.goyal@nxp.com
Cc: stable@dpdk.org

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
 drivers/crypto/dpaa_sec/dpaa_sec.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/crypto/dpaa_sec/dpaa_sec.c b/drivers/crypto/dpaa_sec/dpaa_sec.c
index 3fa88ca968..e117cd77a6 100644
--- a/drivers/crypto/dpaa_sec/dpaa_sec.c
+++ b/drivers/crypto/dpaa_sec/dpaa_sec.c
@@ -1907,13 +1907,12 @@ dpaa_sec_enqueue_burst(void *qp, struct rte_crypto_op **ops,
 			op = *(ops++);
 			if (*dpaa_seqn(op->sym->m_src) != 0) {
 				index = *dpaa_seqn(op->sym->m_src) - 1;
-				if (DPAA_PER_LCORE_DQRR_HELD & (1 << index)) {
+				if (DPAA_PER_LCORE_DQRR_HELD & (UINT64_C(1) << index)) {
 					/* QM_EQCR_DCA_IDXMASK = 0x0f */
 					flags[loop] = ((index & 0x0f) << 8);
 					flags[loop] |= QMAN_ENQUEUE_FLAG_DCA;
 					DPAA_PER_LCORE_DQRR_SIZE--;
-					DPAA_PER_LCORE_DQRR_HELD &=
-								~(1 << index);
+					DPAA_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) << index);
 				}
 			}
 
@@ -3500,7 +3499,7 @@ dpaa_sec_process_atomic_event(void *event,
 	/* Save active dqrr entries */
 	index = ((uintptr_t)dqrr >> 6) & (16/*QM_DQRR_SIZE*/ - 1);
 	DPAA_PER_LCORE_DQRR_SIZE++;
-	DPAA_PER_LCORE_DQRR_HELD |= 1 << index;
+	DPAA_PER_LCORE_DQRR_HELD |= UINT64_C(1) << index;
 	DPAA_PER_LCORE_DQRR_MBUF(index) = ctx->op->sym->m_src;
 	ev->impl_opaque = index + 1;
 	*dpaa_seqn(ctx->op->sym->m_src) = (uint32_t)index + 1;
-- 
2.45.2

[PATCH v2 14/19] event/dpaa: fix bitmask truncation

[Stephen Hemminger]

More bitmask truncation from mask computation.

Fixes: 0ee17f79ebd0 ("event/dpaa: add enqueue/dequeue")
Cc: sunil.kori@nxp.com
Cc: stable@dpdk.org

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
 drivers/event/dpaa/dpaa_eventdev.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/event/dpaa/dpaa_eventdev.c b/drivers/event/dpaa/dpaa_eventdev.c
index 853cc1ecf9..400e0ecd1c 100644
--- a/drivers/event/dpaa/dpaa_eventdev.c
+++ b/drivers/event/dpaa/dpaa_eventdev.c
@@ -102,7 +102,7 @@ dpaa_event_enqueue_burst(void *port, const struct rte_event ev[],
 			qman_dca_index(ev[i].impl_opaque, 0);
 			mbuf = DPAA_PER_LCORE_DQRR_MBUF(i);
 			*dpaa_seqn(mbuf) = DPAA_INVALID_MBUF_SEQN;
-			DPAA_PER_LCORE_DQRR_HELD &= ~(1 << i);
+			DPAA_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) << i);
 			DPAA_PER_LCORE_DQRR_SIZE--;
 			break;
 		default:
@@ -199,11 +199,11 @@ dpaa_event_dequeue_burst(void *port, struct rte_event ev[],
 	/* Check if there are atomic contexts to be released */
 	i = 0;
 	while (DPAA_PER_LCORE_DQRR_SIZE) {
-		if (DPAA_PER_LCORE_DQRR_HELD & (1 << i)) {
+		if (DPAA_PER_LCORE_DQRR_HELD & (UINT64_C(1) << i)) {
 			qman_dca_index(i, 0);
 			mbuf = DPAA_PER_LCORE_DQRR_MBUF(i);
 			*dpaa_seqn(mbuf) = DPAA_INVALID_MBUF_SEQN;
-			DPAA_PER_LCORE_DQRR_HELD &= ~(1 << i);
+			DPAA_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) << i);
 			DPAA_PER_LCORE_DQRR_SIZE--;
 		}
 		i++;
@@ -263,11 +263,11 @@ dpaa_event_dequeue_burst_intr(void *port, struct rte_event ev[],
 	/* Check if there are atomic contexts to be released */
 	i = 0;
 	while (DPAA_PER_LCORE_DQRR_SIZE) {
-		if (DPAA_PER_LCORE_DQRR_HELD & (1 << i)) {
+		if (DPAA_PER_LCORE_DQRR_HELD & (UINT64_C(1) << i)) {
 			qman_dca_index(i, 0);
 			mbuf = DPAA_PER_LCORE_DQRR_MBUF(i);
 			*dpaa_seqn(mbuf) = DPAA_INVALID_MBUF_SEQN;
-			DPAA_PER_LCORE_DQRR_HELD &= ~(1 << i);
+			DPAA_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) << i);
 			DPAA_PER_LCORE_DQRR_SIZE--;
 		}
 		i++;
-- 
2.45.2

[PATCH v2 15/19] net/dpaa: fix bitmask truncation

[Stephen Hemminger]

The dqrr_held mask is 64 bit but updates were getting truncated
because 1 is of type int (32 bit) and the result shift of int is of
type int (32 bit); therefore any value >= 32 would get truncated.

Link: https://pvs-studio.com/en/blog/posts/cpp/1183/

Fixes: 5e7455931442 ("net/dpaa: support Rx queue configurations with eventdev")
Cc: sunil.kori@nxp.com
Cc: stable@dpdk.org

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
 drivers/net/dpaa/dpaa_rxtx.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/net/dpaa/dpaa_rxtx.c b/drivers/net/dpaa/dpaa_rxtx.c
index 247e7b92ba..05bd73becf 100644
--- a/drivers/net/dpaa/dpaa_rxtx.c
+++ b/drivers/net/dpaa/dpaa_rxtx.c
@@ -842,7 +842,7 @@ dpaa_rx_cb_atomic(void *event,
 	/* Save active dqrr entries */
 	index = DQRR_PTR2IDX(dqrr);
 	DPAA_PER_LCORE_DQRR_SIZE++;
-	DPAA_PER_LCORE_DQRR_HELD |= 1 << index;
+	DPAA_PER_LCORE_DQRR_HELD |= UINT64_C(1) << index;
 	DPAA_PER_LCORE_DQRR_MBUF(index) = mbuf;
 	ev->impl_opaque = index + 1;
 	*dpaa_seqn(mbuf) = (uint32_t)index + 1;
@@ -1338,13 +1338,12 @@ dpaa_eth_queue_tx(void *q, struct rte_mbuf **bufs, uint16_t nb_bufs)
 			seqn = *dpaa_seqn(mbuf);
 			if (seqn != DPAA_INVALID_MBUF_SEQN) {
 				index = seqn - 1;
-				if (DPAA_PER_LCORE_DQRR_HELD & (1 << index)) {
+				if (DPAA_PER_LCORE_DQRR_HELD & (UINT64_C(1) << index)) {
 					flags[loop] =
 					   ((index & QM_EQCR_DCA_IDXMASK) << 8);
 					flags[loop] |= QMAN_ENQUEUE_FLAG_DCA;
 					DPAA_PER_LCORE_DQRR_SIZE--;
-					DPAA_PER_LCORE_DQRR_HELD &=
-								~(1 << index);
+					DPAA_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) << index);
 				}
 			}
 
-- 
2.45.2

[PATCH v2 16/19] net/dpaa2: fix bitmask truncation

[Stephen Hemminger]

The dqrr_held mask is 64 bit but updates were getting truncated
because 1 is of type int (32 bit) and the result shift of int is of
type int (32 bit); therefore any value >= 32 would get truncated.

Link: https://pvs-studio.com/en/blog/posts/cpp/1183/

Fixes: 2d3788631862 ("net/dpaa2: support atomic queues")
Cc: nipun.gupta@nxp.com
Cc: stable@dpdk.org

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
 drivers/net/dpaa2/dpaa2_rxtx.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/net/dpaa2/dpaa2_rxtx.c b/drivers/net/dpaa2/dpaa2_rxtx.c
index e3b6c7e460..e253bccecd 100644
--- a/drivers/net/dpaa2/dpaa2_rxtx.c
+++ b/drivers/net/dpaa2/dpaa2_rxtx.c
@@ -933,7 +933,7 @@ dpaa2_dev_process_atomic_event(struct qbman_swp *swp __rte_unused,
 	dqrr_index = qbman_get_dqrr_idx(dq);
 	*dpaa2_seqn(ev->mbuf) = dqrr_index + 1;
 	DPAA2_PER_LCORE_DQRR_SIZE++;
-	DPAA2_PER_LCORE_DQRR_HELD |= 1 << dqrr_index;
+	DPAA2_PER_LCORE_DQRR_HELD |= UINT64_C(1) << dqrr_index;
 	DPAA2_PER_LCORE_DQRR_MBUF(dqrr_index) = ev->mbuf;
 }
 
@@ -1317,7 +1317,7 @@ dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
 				flags[loop] = QBMAN_ENQUEUE_FLAG_DCA |
 						dqrr_index;
 				DPAA2_PER_LCORE_DQRR_SIZE--;
-				DPAA2_PER_LCORE_DQRR_HELD &= ~(1 << dqrr_index);
+				DPAA2_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) << dqrr_index);
 				*dpaa2_seqn(*bufs) = DPAA2_INVALID_MBUF_SEQN;
 			}
 
@@ -1575,7 +1575,7 @@ dpaa2_set_enqueue_descriptor(struct dpaa2_queue *dpaa2_q,
 		dq_idx = *dpaa2_seqn(m) - 1;
 		qbman_eq_desc_set_dca(eqdesc, 1, dq_idx, 0);
 		DPAA2_PER_LCORE_DQRR_SIZE--;
-		DPAA2_PER_LCORE_DQRR_HELD &= ~(1 << dq_idx);
+		DPAA2_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) << dq_idx);
 	}
 	*dpaa2_seqn(m) = DPAA2_INVALID_MBUF_SEQN;
 }
-- 
2.45.2

[PATCH v2 17/19] net/qede: don't use same loop variable twice

[Stephen Hemminger]

Using variable in outer loop, and inner loop is obvious bug.
This bug is in base code, so likely on other platforms as well.

Link: https://pvs-studio.com/en/blog/posts/cpp/1183/
Fixes: 81dba2b2ff61 ("net/qede/base: add LLDP support")
Cc: rasesh.mody@cavium.com
Cc: stable@dpdk.org

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
---
 drivers/net/qede/base/ecore_dcbx.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/net/qede/base/ecore_dcbx.c b/drivers/net/qede/base/ecore_dcbx.c
index 31234f18cf..72bbedd65a 100644
--- a/drivers/net/qede/base/ecore_dcbx.c
+++ b/drivers/net/qede/base/ecore_dcbx.c
@@ -1363,7 +1363,7 @@ ecore_lldp_mib_update_event(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
 	struct ecore_dcbx_mib_meta_data data;
 	enum _ecore_status_t rc = ECORE_SUCCESS;
 	struct lldp_received_tlvs_s tlvs;
-	int i;
+	int i, j;
 
 	for (i = 0; i < LLDP_MAX_LLDP_AGENTS; i++) {
 		OSAL_MEM_ZERO(&data, sizeof(data));
@@ -1381,9 +1381,9 @@ ecore_lldp_mib_update_event(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
 		if (!tlvs.length)
 			continue;
 
-		for (i = 0; i < MAX_TLV_BUFFER; i++)
-			tlvs.tlvs_buffer[i] =
-				OSAL_CPU_TO_BE32(tlvs.tlvs_buffer[i]);
+		for (j = 0; j < MAX_TLV_BUFFER; j++)
+			tlvs.tlvs_buffer[j] =
+				OSAL_CPU_TO_BE32(tlvs.tlvs_buffer[j]);
 
 		OSAL_LLDP_RX_TLVS(p_hwfn, tlvs.tlvs_buffer, tlvs.length);
 	}
-- 
2.45.2

[PATCH v2 18/19] examples/l3fwd: fix operator precedence bugs

[Stephen Hemminger]

The expression:

  if ((socketid = rte_lcore_to_socket_id(lcore) != 0) &&

gets evaluated as sockeid = (rte_lcore_to_socket_id(lcore) != 0)
which is not what was intended. This is goes all the way back
to first release.

Link: https://pvs-studio.com/en/blog/posts/cpp/1183/
Fixes: af75078fece3 ("first public release")
Cc: stable@dpdk.org

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
---
 examples/l3fwd-power/main.c | 4 ++--
 examples/l3fwd/main.c       | 5 +++--
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/examples/l3fwd-power/main.c b/examples/l3fwd-power/main.c
index ae8b55924e..7957ea6c95 100644
--- a/examples/l3fwd-power/main.c
+++ b/examples/l3fwd-power/main.c
@@ -1412,8 +1412,8 @@ check_lcore_params(void)
 							"mask\n", lcore);
 			return -1;
 		}
-		if ((socketid = rte_lcore_to_socket_id(lcore) != 0) &&
-							(numa_on == 0)) {
+		socketid = rte_lcore_to_socket_id(lcore);
+		if (socketid != 0 && numa_on == 0) {
 			printf("warning: lcore %u is on socket %d with numa "
 						"off\n", lcore, socketid);
 		}
diff --git a/examples/l3fwd/main.c b/examples/l3fwd/main.c
index 6e2155e005..14076e07cc 100644
--- a/examples/l3fwd/main.c
+++ b/examples/l3fwd/main.c
@@ -307,8 +307,9 @@ check_lcore_params(void)
 			printf("error: lcore %u is not enabled in lcore mask\n", lcore);
 			return -1;
 		}
-		if ((socketid = rte_lcore_to_socket_id(lcore) != 0) &&
-			(numa_on == 0)) {
+
+		socketid = rte_lcore_to_socket_id(lcore);
+		if (socketid != 0 && numa_on == 0) {
 			printf("warning: lcore %u is on socket %d with numa off\n",
 				lcore, socketid);
 		}
-- 
2.45.2