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From: Tejasree Kondoj <ktejasree@marvell.com>
To: Akhil Goyal <gakhil@marvell.com>
Cc: Nithinsen Kaithakadan <nkaithakadan@marvell.com>,
	Anoob Joseph <anoobj@marvell.com>,
	Rupesh Chiluka <rchiluka@marvell.com>,
	"Vidya Sagar Velumuri" <vvelumuri@marvell.com>, <dev@dpdk.org>,
	<stable@dpdk.org>
Subject: [PATCH v2 6/7] common/cnxk: update qsize in CPT iq enable
Date: Mon, 9 Jun 2025 16:10:37 +0530	[thread overview]
Message-ID: <20250609104038.3102767-7-ktejasree@marvell.com> (raw)
In-Reply-To: <20250609104038.3102767-1-ktejasree@marvell.com>

From: Nithinsen Kaithakadan <nkaithakadan@marvell.com>

Reconfigure qsize in each CPT iq enable call.

Fixes: 3bf87839559 ("common/cnxk: move instruction queue enable to ROC")
Cc: stable@dpdk.org

Signed-off-by: Nithinsen Kaithakadan <nkaithakadan@marvell.com>
---
 drivers/common/cnxk/roc_cpt.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c
index b4bf0ccd64..d1ba2b8858 100644
--- a/drivers/common/cnxk/roc_cpt.c
+++ b/drivers/common/cnxk/roc_cpt.c
@@ -1125,9 +1125,14 @@ roc_cpt_iq_disable(struct roc_cpt_lf *lf)
 void
 roc_cpt_iq_enable(struct roc_cpt_lf *lf)
 {
+	union cpt_lf_q_size lf_q_size;
 	union cpt_lf_inprog lf_inprog;
 	union cpt_lf_ctl lf_ctl;
 
+	/* Reconfigure the QSIZE register to ensure NQ_PTR and DQ_PTR are reset */
+	lf_q_size.u = plt_read64(lf->rbase + CPT_LF_Q_SIZE);
+	plt_write64(lf_q_size.u, lf->rbase + CPT_LF_Q_SIZE);
+
 	/* Disable command queue */
 	roc_cpt_iq_disable(lf);
 
-- 
2.25.1


      parent reply	other threads:[~2025-06-09 10:41 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20250609104038.3102767-1-ktejasree@marvell.com>
2025-06-09 10:40 ` [PATCH v2 1/7] crypto/cnxk: fix compilation error Tejasree Kondoj
2025-06-09 10:40 ` [PATCH v2 2/7] common/cnxk: fix salt handling with aes-ctr Tejasree Kondoj
2025-06-09 10:40 ` Tejasree Kondoj [this message]

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