patches for DPDK stable branches
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From: Xueming Li <xuemingl@nvidia.com>
To: Arkadiusz Kusztal <arkadiuszx.kusztal@intel.com>
Cc: Xueming Li <xuemingl@nvidia.com>, dpdk stable <stable@dpdk.org>
Subject: patch 'crypto/qat: fix out-of-place chain/cipher/auth headers' has been queued to stable release 23.11.5
Date: Thu, 26 Jun 2025 20:00:40 +0800	[thread overview]
Message-ID: <20250626120145.27369-21-xuemingl@nvidia.com> (raw)
In-Reply-To: <20250626120145.27369-1-xuemingl@nvidia.com>

Hi,

FYI, your patch has been queued to stable release 23.11.5

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 06/28/25. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://git.dpdk.org/dpdk-stable/log/?h=23.11-staging

This queued commit can be viewed at:
https://git.dpdk.org/dpdk-stable/commit/?h=23.11-staging&id=34f3447290892361ff0cc71c3b3d407b2f0a5d1d

Thanks.

Xueming Li <xuemingl@nvidia.com>

---
From 34f3447290892361ff0cc71c3b3d407b2f0a5d1d Mon Sep 17 00:00:00 2001
From: Arkadiusz Kusztal <arkadiuszx.kusztal@intel.com>
Date: Mon, 28 Apr 2025 06:30:41 +0000
Subject: [PATCH] crypto/qat: fix out-of-place chain/cipher/auth headers
Cc: Xueming Li <xuemingl@nvidia.com>

[ upstream commit 317d05f3721c9a740614adf77aa89d00d5302cf7 ]

This commit fixes a problem with overwriting data in the OOP header
in RAW API crypto processing when using chain, cipher and auth algorithms.

Fixes: 85fec6fd9674 ("crypto/qat: unify raw data path functions")

Signed-off-by: Arkadiusz Kusztal <arkadiuszx.kusztal@intel.com>
---
 drivers/crypto/qat/dev/qat_crypto_pmd_gens.h | 146 +++++++++++++++++++
 drivers/crypto/qat/dev/qat_sym_pmd_gen1.c    |  40 +++--
 2 files changed, 171 insertions(+), 15 deletions(-)

diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h
index a817c2bbb7..1c6ef0aae9 100644
--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h
+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h
@@ -275,6 +275,152 @@ done:
 	return src_tot_length;
 }
 
+struct qat_sym_req_mid_info {
+	uint32_t data_len;
+	union rte_crypto_sym_ofs ofs;
+};
+
+static inline
+struct qat_sym_req_mid_info qat_sym_req_mid_set(
+	int *error, struct icp_qat_fw_la_bulk_req *const req,
+	struct qat_sym_op_cookie *const cookie, const void *const opaque,
+	const struct rte_crypto_sgl *sgl_src, const struct rte_crypto_sgl *sgl_dst,
+	const union rte_crypto_sym_ofs ofs)
+{
+	struct qat_sym_req_mid_info info = { };  /* Returned value */
+	uint32_t src_tot_length = 0;
+	uint32_t dst_tot_length = 0; /* Used only for input validity checks */
+	uint32_t src_length = 0;
+	uint32_t dst_length = 0;
+	uint64_t src_data_addr = 0;
+	uint64_t dst_data_addr = 0;
+	union rte_crypto_sym_ofs out_ofs = ofs;
+	const struct rte_crypto_vec * const vec_src = sgl_src->vec;
+	const struct rte_crypto_vec * const vec_dst = sgl_dst->vec;
+	const uint32_t n_src = sgl_src->num;
+	const uint32_t n_dst = sgl_dst->num;
+	const uint16_t offset = RTE_MIN(ofs.ofs.cipher.head, ofs.ofs.auth.head);
+	const uint8_t is_flat = !(n_src > 1 || n_dst > 1); /* Flat buffer or the SGL */
+	const uint8_t is_in_place = !n_dst; /* In-place or out-of-place */
+
+	*error = 0;
+	if (unlikely((n_src < 1 || n_src > QAT_SYM_SGL_MAX_NUMBER) ||
+			n_dst > QAT_SYM_SGL_MAX_NUMBER)) {
+		QAT_LOG(DEBUG,
+			"Invalid number of sgls, source no: %u, dst no: %u, opaque: %p",
+			n_src, n_dst, opaque);
+		*error = -1;
+		return info;
+	}
+
+	/* --- Flat buffer --- */
+	if (is_flat) {
+		src_data_addr = vec_src->iova;
+		dst_data_addr = vec_src->iova;
+		src_length = vec_src->len;
+		dst_length = vec_src->len;
+
+		if (is_in_place)
+			goto done;
+		/* Out-of-place
+		 * If OOP, we need to keep in mind that offset needs to
+		 * start where the aead starts
+		 */
+		dst_length = vec_dst->len;
+		/* Comparison between different types, intentional */
+		if (unlikely(offset > src_length || offset > dst_length)) {
+			QAT_LOG(DEBUG,
+				"Invalid size of the vector parameters, source length: %u, dst length: %u, opaque: %p",
+				src_length, dst_length, opaque);
+			*error = -1;
+			return info;
+		}
+		out_ofs.ofs.cipher.head -= offset;
+		out_ofs.ofs.auth.head -= offset;
+		src_data_addr += offset;
+		dst_data_addr = vec_dst->iova + offset;
+		src_length -= offset;
+		dst_length -= offset;
+		src_tot_length = src_length;
+		dst_tot_length = dst_length;
+		goto check;
+	}
+
+	/* --- Scatter-gather list --- */
+	struct qat_sgl * const qat_sgl_src = (struct qat_sgl *)&cookie->qat_sgl_src;
+	uint16_t i;
+
+	ICP_QAT_FW_COMN_PTR_TYPE_SET(req->comn_hdr.comn_req_flags,
+		QAT_COMN_PTR_TYPE_SGL);
+	qat_sgl_src->num_bufs = n_src;
+	src_data_addr = cookie->qat_sgl_src_phys_addr;
+	/* Fill all the source buffers but the first one */
+	for (i = 1; i < n_src; i++) {
+		qat_sgl_src->buffers[i].len = (vec_src + i)->len;
+		qat_sgl_src->buffers[i].addr = (vec_src + i)->iova;
+		src_tot_length += qat_sgl_src->buffers[i].len;
+	}
+
+	if (is_in_place) {
+		/* SGL source first entry, no OOP */
+		qat_sgl_src->buffers[0].len = vec_src->len;
+		qat_sgl_src->buffers[0].addr = vec_src->iova;
+		dst_data_addr = src_data_addr;
+		goto done;
+	}
+	/* Out-of-place */
+	struct qat_sgl * const qat_sgl_dst =
+			(struct qat_sgl *)&cookie->qat_sgl_dst;
+	/*
+	 * Offset reaching outside of the first buffer is not supported (RAW api).
+	 * Integer promotion here, but it does not bother this time
+	 */
+	if (unlikely(offset > vec_src->len || offset > vec_dst->len)) {
+		QAT_LOG(DEBUG,
+			"Invalid size of the vector parameters, source length: %u, dst length: %u, opaque: %p",
+			vec_src->len, vec_dst->len, opaque);
+		*error = -1;
+		return info;
+	}
+	out_ofs.ofs.cipher.head -= offset;
+	out_ofs.ofs.auth.head -= offset;
+	/* SGL source first entry, adjusted to OOP offsets */
+	qat_sgl_src->buffers[0].addr = vec_src->iova + offset;
+	qat_sgl_src->buffers[0].len = vec_src->len - offset;
+	/* SGL destination first entry, adjusted to OOP offsets */
+	qat_sgl_dst->buffers[0].addr = vec_dst->iova + offset;
+	qat_sgl_dst->buffers[0].len = vec_dst->len - offset;
+	/* Fill the remaining destination buffers */
+	for (i = 1; i < n_dst; i++) {
+		qat_sgl_dst->buffers[i].len = (vec_dst + i)->len;
+		qat_sgl_dst->buffers[i].addr = (vec_dst + i)->iova;
+		dst_tot_length += qat_sgl_dst->buffers[i].len;
+	}
+	dst_tot_length += qat_sgl_dst->buffers[0].len;
+	qat_sgl_dst->num_bufs = n_dst;
+	dst_data_addr = cookie->qat_sgl_dst_phys_addr;
+
+check:	/* If error, return directly. If success, jump to one of these labels */
+	if (src_tot_length != dst_tot_length) {
+		QAT_LOG(DEBUG,
+			"Source length is not equal to the destination length %u, dst no: %u, opaque: %p",
+			src_tot_length, dst_tot_length, opaque);
+		*error = -1;
+		return info;
+	}
+done:
+	req->comn_mid.opaque_data = (uintptr_t)opaque;
+	req->comn_mid.src_data_addr = src_data_addr;
+	req->comn_mid.dest_data_addr = dst_data_addr;
+	req->comn_mid.src_length = src_length;
+	req->comn_mid.dst_length = dst_length;
+
+	info.data_len = src_tot_length;
+	info.ofs = out_ofs;
+
+	return info;
+}
+
 static __rte_always_inline int32_t
 qat_sym_build_req_set_data(struct icp_qat_fw_la_bulk_req *req,
 		void *opaque, struct qat_sym_op_cookie *cookie,
diff --git a/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c b/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c
index b06514cd62..1e7c35afed 100644
--- a/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c
+++ b/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c
@@ -544,16 +544,20 @@ qat_sym_dp_enqueue_cipher_jobs_gen1(void *qp_data, uint8_t *drv_ctx,
 	for (i = 0; i < n; i++) {
 		struct qat_sym_op_cookie *cookie =
 			qp->op_cookies[tail >> tx_queue->trailz];
+		struct qat_sym_req_mid_info info = { };
+		union rte_crypto_sym_ofs temp_ofs = ofs;
+		int error = 0;
 
+		temp_ofs.ofs.auth = temp_ofs.ofs.cipher;
 		req  = (struct icp_qat_fw_la_bulk_req *)(
 			(uint8_t *)tx_queue->base_addr + tail);
 		rte_mov128((uint8_t *)req, (const uint8_t *)&(ctx->fw_req));
 
 		if (vec->dest_sgl) {
-			data_len = qat_sym_build_req_set_data(req,
-				user_data[i], cookie,
-				vec->src_sgl[i].vec, vec->src_sgl[i].num,
-				vec->dest_sgl[i].vec, vec->dest_sgl[i].num);
+			info = qat_sym_req_mid_set(&error, req, cookie, user_data[i],
+				&vec->src_sgl[i], &vec->dest_sgl[i], temp_ofs);
+			data_len = info.data_len;
+			ofs = info.ofs;
 		} else {
 			data_len = qat_sym_build_req_set_data(req,
 				user_data[i], cookie,
@@ -561,7 +565,7 @@ qat_sym_dp_enqueue_cipher_jobs_gen1(void *qp_data, uint8_t *drv_ctx,
 				vec->src_sgl[i].num, NULL, 0);
 		}
 
-		if (unlikely(data_len < 0))
+		if (unlikely(data_len < 0 || error))
 			break;
 		enqueue_one_cipher_job_gen1(ctx, req, &vec->iv[i], ofs,
 			(uint32_t)data_len, cookie);
@@ -658,16 +662,20 @@ qat_sym_dp_enqueue_auth_jobs_gen1(void *qp_data, uint8_t *drv_ctx,
 	for (i = 0; i < n; i++) {
 		struct qat_sym_op_cookie *cookie =
 			qp->op_cookies[tail >> tx_queue->trailz];
+		struct qat_sym_req_mid_info info = { };
+		union rte_crypto_sym_ofs temp_ofs = ofs;
+		int error = 0;
 
+		temp_ofs.ofs.cipher = temp_ofs.ofs.auth;
 		req  = (struct icp_qat_fw_la_bulk_req *)(
 			(uint8_t *)tx_queue->base_addr + tail);
 		rte_mov128((uint8_t *)req, (const uint8_t *)&(ctx->fw_req));
 
 		if (vec->dest_sgl) {
-			data_len = qat_sym_build_req_set_data(req,
-				user_data[i], cookie,
-				vec->src_sgl[i].vec, vec->src_sgl[i].num,
-				vec->dest_sgl[i].vec, vec->dest_sgl[i].num);
+			info = qat_sym_req_mid_set(&error, req, cookie, user_data[i],
+				&vec->src_sgl[i], &vec->dest_sgl[i], temp_ofs);
+			data_len = info.data_len;
+			ofs = info.ofs;
 		} else {
 			data_len = qat_sym_build_req_set_data(req,
 				user_data[i], cookie,
@@ -675,7 +683,7 @@ qat_sym_dp_enqueue_auth_jobs_gen1(void *qp_data, uint8_t *drv_ctx,
 				vec->src_sgl[i].num, NULL, 0);
 		}
 
-		if (unlikely(data_len < 0))
+		if (unlikely(data_len < 0 || error))
 			break;
 
 		if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL) {
@@ -781,16 +789,18 @@ qat_sym_dp_enqueue_chain_jobs_gen1(void *qp_data, uint8_t *drv_ctx,
 	for (i = 0; i < n; i++) {
 		struct qat_sym_op_cookie *cookie =
 			qp->op_cookies[tail >> tx_queue->trailz];
+		struct qat_sym_req_mid_info info = { };
+		int error = 0;
 
 		req  = (struct icp_qat_fw_la_bulk_req *)(
 			(uint8_t *)tx_queue->base_addr + tail);
 		rte_mov128((uint8_t *)req, (const uint8_t *)&(ctx->fw_req));
 
 		if (vec->dest_sgl) {
-			data_len = qat_sym_build_req_set_data(req,
-				user_data[i], cookie,
-				vec->src_sgl[i].vec, vec->src_sgl[i].num,
-				vec->dest_sgl[i].vec, vec->dest_sgl[i].num);
+			info = qat_sym_req_mid_set(&error, req, cookie, user_data[i],
+				&vec->src_sgl[i], &vec->dest_sgl[i], ofs);
+			data_len = info.data_len;
+			ofs = info.ofs;
 		} else {
 			data_len = qat_sym_build_req_set_data(req,
 				user_data[i], cookie,
@@ -798,7 +808,7 @@ qat_sym_dp_enqueue_chain_jobs_gen1(void *qp_data, uint8_t *drv_ctx,
 				vec->src_sgl[i].num, NULL, 0);
 		}
 
-		if (unlikely(data_len < 0))
+		if (unlikely(data_len < 0 || error))
 			break;
 
 		if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL) {
-- 
2.34.1

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2025-06-26 19:59:18.665600991 +0800
+++ 0020-crypto-qat-fix-out-of-place-chain-cipher-auth-header.patch	2025-06-26 19:59:17.234418050 +0800
@@ -1 +1 @@
-From 317d05f3721c9a740614adf77aa89d00d5302cf7 Mon Sep 17 00:00:00 2001
+From 34f3447290892361ff0cc71c3b3d407b2f0a5d1d Mon Sep 17 00:00:00 2001
@@ -4,0 +5,3 @@
+Cc: Xueming Li <xuemingl@nvidia.com>
+
+[ upstream commit 317d05f3721c9a740614adf77aa89d00d5302cf7 ]
@@ -10 +12,0 @@
-Cc: stable@dpdk.org
@@ -19 +21 @@
-index c447f2cb45..846636f57d 100644
+index a817c2bbb7..1c6ef0aae9 100644
@@ -22 +24 @@
-@@ -280,6 +280,152 @@ done:
+@@ -275,6 +275,152 @@ done:
@@ -176 +178 @@
-index 3976d03179..561166203c 100644
+index b06514cd62..1e7c35afed 100644
@@ -179 +181 @@
-@@ -567,16 +567,20 @@ qat_sym_dp_enqueue_cipher_jobs_gen1(void *qp_data, uint8_t *drv_ctx,
+@@ -544,16 +544,20 @@ qat_sym_dp_enqueue_cipher_jobs_gen1(void *qp_data, uint8_t *drv_ctx,
@@ -204 +206 @@
-@@ -584,7 +588,7 @@ qat_sym_dp_enqueue_cipher_jobs_gen1(void *qp_data, uint8_t *drv_ctx,
+@@ -561,7 +565,7 @@ qat_sym_dp_enqueue_cipher_jobs_gen1(void *qp_data, uint8_t *drv_ctx,
@@ -211,3 +213,3 @@
- 
- 		if (ctx->is_zuc256)
-@@ -688,16 +692,20 @@ qat_sym_dp_enqueue_auth_jobs_gen1(void *qp_data, uint8_t *drv_ctx,
+ 		enqueue_one_cipher_job_gen1(ctx, req, &vec->iv[i], ofs,
+ 			(uint32_t)data_len, cookie);
+@@ -658,16 +662,20 @@ qat_sym_dp_enqueue_auth_jobs_gen1(void *qp_data, uint8_t *drv_ctx,
@@ -238 +240 @@
-@@ -705,7 +713,7 @@ qat_sym_dp_enqueue_auth_jobs_gen1(void *qp_data, uint8_t *drv_ctx,
+@@ -675,7 +683,7 @@ qat_sym_dp_enqueue_auth_jobs_gen1(void *qp_data, uint8_t *drv_ctx,
@@ -246,2 +248,2 @@
- 		if (ctx->is_zuc256)
-@@ -819,16 +827,18 @@ qat_sym_dp_enqueue_chain_jobs_gen1(void *qp_data, uint8_t *drv_ctx,
+ 		if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL) {
+@@ -781,16 +789,18 @@ qat_sym_dp_enqueue_chain_jobs_gen1(void *qp_data, uint8_t *drv_ctx,
@@ -270 +272 @@
-@@ -836,7 +846,7 @@ qat_sym_dp_enqueue_chain_jobs_gen1(void *qp_data, uint8_t *drv_ctx,
+@@ -798,7 +808,7 @@ qat_sym_dp_enqueue_chain_jobs_gen1(void *qp_data, uint8_t *drv_ctx,
@@ -278 +280 @@
- 		if (ctx->is_zuc256) {
+ 		if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL) {

  parent reply	other threads:[~2025-06-26 12:04 UTC|newest]

Thread overview: 86+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-26 12:00 patch " Xueming Li
2025-06-26 12:00 ` patch 'ethdev: convert string initialization' " Xueming Li
2025-06-26 12:00 ` patch 'net/fm10k/base: fix compilation warnings' " Xueming Li
2025-06-26 12:00 ` patch 'net/ixgbe/base: correct definition of endianness macro' " Xueming Li
2025-06-26 12:00 ` patch 'net/ixgbe/base: fix compilation warnings' " Xueming Li
2025-06-26 12:00 ` patch 'net/i40e/base: fix unused value " Xueming Li
2025-06-26 12:00 ` patch 'net/i40e/base: fix compiler " Xueming Li
2025-06-26 12:00 ` patch 'acl: fix build with GCC 15 on aarch64' " Xueming Li
2025-06-26 12:00 ` patch 'eal/linux: improve ASLR check' " Xueming Li
2025-06-26 12:00 ` patch 'net/e1000: fix xstats name' " Xueming Li
2025-06-26 12:00 ` patch 'net/e1000: fix EEPROM dump' " Xueming Li
2025-06-26 12:00 ` patch 'net/ixgbe: enable ethertype filter for E610' " Xueming Li
2025-06-26 12:00 ` patch 'net/ixgbe: fix port mask default value in filter' " Xueming Li
2025-06-26 12:00 ` patch 'net/e1000: fix igb Tx queue offloads capability' " Xueming Li
2025-06-26 12:00 ` patch 'net/ice: fix flow creation failure' " Xueming Li
2025-06-26 12:00 ` patch 'vhost: fix wrapping on control virtqueue rings' " Xueming Li
2025-06-26 12:00 ` patch 'vhost/crypto: fix cipher data length' " Xueming Li
2025-06-26 12:00 ` patch 'crypto/virtio: fix cipher data source " Xueming Li
2025-06-26 12:00 ` patch 'app/crypto-perf: fix AAD offset alignment' " Xueming Li
2025-06-26 12:00 ` patch 'crypto/qat: fix out-of-place header bytes in AEAD raw API' " Xueming Li
2025-06-26 12:00 ` Xueming Li [this message]
2025-06-26 12:00 ` patch 'net/mlx5: fix header modify action on group 0' " Xueming Li
2025-06-26 12:00 ` patch 'net/mlx5: validate GTP PSC QFI width' " Xueming Li
2025-06-26 12:00 ` patch 'net/mlx5: fix counter service cleanup on init failure' " Xueming Li
2025-06-26 12:00 ` patch 'net/mlx5/hws: fix send queue drain on FW WQE destroy' " Xueming Li
2025-06-26 12:00 ` patch 'net/mlx5: remove unsupported flow meter action in HWS' " Xueming Li
2025-06-26 12:00 ` patch 'net/mlx5: fix maximal queue size query' " Xueming Li
2025-06-26 12:00 ` patch 'net/mlx5: fix mark action with shared Rx queue' " Xueming Li
2025-06-26 12:00 ` patch 'net/mlx5: align PF and VF/SF MAC address handling' " Xueming Li
2025-06-26 12:00 ` patch 'net/sfc: fix action order on start failure' " Xueming Li
2025-06-26 12:00 ` patch 'net/nfp: fix crash with null RSS hash key' " Xueming Li
2025-06-26 12:00 ` patch 'net/nfp: fix hash key length logic' " Xueming Li
2025-06-26 12:00 ` patch 'app/testpmd: fix RSS hash key update' " Xueming Li
2025-06-26 12:00 ` patch 'net/af_xdp: fix use after free in zero-copy Tx' " Xueming Li
2025-06-26 12:00 ` patch 'net/hns3: fix integer overflow in interrupt unmap' " Xueming Li
2025-06-26 12:00 ` patch 'net/hns3: fix memory leak on failure' " Xueming Li
2025-06-26 12:00 ` patch 'net/hns3: fix extra wait for link up' " Xueming Li
2025-06-26 12:00 ` patch 'net/hns3: fix memory leak for indirect flow action' " Xueming Li
2025-06-26 12:00 ` patch 'net/hns3: fix interrupt rollback' " Xueming Li
2025-06-26 12:00 ` patch 'net/hns3: fix divide by zero' " Xueming Li
2025-06-26 12:01 ` patch 'net/hns3: fix resources release on reset' " Xueming Li
2025-06-26 12:01 ` patch 'net/nfp: standardize NFD3 Tx descriptor endianness' " Xueming Li
2025-06-26 12:01 ` patch 'net/nfp: standardize NFDk " Xueming Li
2025-06-26 12:01 ` patch 'net/qede: fix use after free' " Xueming Li
2025-06-26 12:01 ` patch 'bus/fslmc: " Xueming Li
2025-06-26 12:01 ` patch 'net/null: fix packet copy' " Xueming Li
2025-06-26 12:01 ` patch 'bus/vmbus: align ring buffer data to page boundary' " Xueming Li
2025-06-26 12:01 ` patch 'bus/vmbus: use Hyper-V page size' " Xueming Li
2025-06-26 12:01 ` patch 'net/netvsc: " Xueming Li
2025-06-26 12:01 ` patch 'net/netvsc: add stats counters from VF' " Xueming Li
2025-06-26 12:01 ` patch 'app/testpmd: relax number of TCs in DCB command' " Xueming Li
2025-06-26 12:01 ` patch 'net/mana: check vendor ID when probing RDMA device' " Xueming Li
2025-06-26 12:01 ` patch 'net/hns3: fix CRC data segment' " Xueming Li
2025-06-26 12:01 ` patch 'net/tap: fix qdisc add failure handling' " Xueming Li
2025-06-26 12:01 ` patch 'net/mlx5: fix VLAN stripping on hairpin queue' " Xueming Li
2025-06-26 12:01 ` patch 'mem: fix lockup on address space shortage' " Xueming Li
2025-06-26 12:01 ` patch 'test/malloc: improve resiliency' " Xueming Li
2025-06-26 12:01 ` patch 'trace: fix overflow in per-lcore trace buffer' " Xueming Li
2025-06-26 12:01 ` patch 'common/cnxk: fix E-tag pattern parsing' " Xueming Li
2025-06-26 12:01 ` patch 'common/cnxk: fix CQ tail drop' " Xueming Li
2025-06-26 12:01 ` patch 'net/cnxk: fix descriptor count update on reconfig' " Xueming Li
2025-06-26 12:01 ` patch 'ethdev: fix error struct in flow configure' " Xueming Li
2025-06-26 12:01 ` patch 'net/ice/base: fix integer overflow' " Xueming Li
2025-06-26 12:01 ` patch 'net/ice/base: fix typo in device ID description' " Xueming Li
2025-06-26 12:01 ` patch 'common/dpaax: fix PDCP key command race condition' " Xueming Li
2025-06-26 12:01 ` patch 'common/dpaax: fix PDCP AES only 12-bit SN' " Xueming Li
2025-06-26 12:01 ` patch 'crypto/dpaa2_sec: fix uninitialized variable' " Xueming Li
2025-06-26 12:01 ` patch 'crypto/virtio: add request check on request side' " Xueming Li
2025-06-26 12:01 ` patch 'crypto/virtio: fix driver cleanup' " Xueming Li
2025-06-26 12:01 ` patch 'crypto/virtio: fix driver ID' " Xueming Li
2025-06-26 12:01 ` patch 'ethdev: keep promiscuous/allmulti value before disabling' " Xueming Li
2025-06-26 12:01 ` patch 'eal: fix return value of lcore role' " Xueming Li
2025-06-26 12:01 ` patch 'eal: warn if no lcore is available' " Xueming Li
2025-06-26 12:01 ` patch 'test/lcore: fix race in per-lcore test' " Xueming Li
2025-06-26 12:01 ` patch 'bus: cleanup device lists' " Xueming Li
2025-06-26 12:01 ` patch 'eal/linux: unregister alarm callback before free' " Xueming Li
2025-06-26 12:01 ` patch 'eal/freebsd: " Xueming Li
2025-06-26 12:01 ` patch 'bus/pci/bsd: fix device existence check' " Xueming Li
2025-06-26 12:01 ` patch 'power/intel_uncore: fix crash closing uninitialized driver' " Xueming Li
2025-06-26 12:01 ` patch 'crypto/qat: fix size calculation for memset' " Xueming Li
2025-06-26 12:01 ` patch 'net/mlx5: avoid setting kernel MTU if not needed' " Xueming Li
2025-06-26 12:01 ` patch 'doc: add kernel options required for mlx5' " Xueming Li
2025-06-26 12:01 ` patch 'net/mlx5: fix hypervisor detection in VLAN workaround' " Xueming Li
2025-06-26 12:01 ` patch 'net/hns3: check requirement for hardware GRO' " Xueming Li
2025-06-26 12:01 ` patch 'net/hns3: allow Tx vector when fast free not enabled' " Xueming Li
2025-06-26 12:01 ` patch 'net/hns3: allow Rx vector mode with VLAN filter' " Xueming Li

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