patches for DPDK stable branches
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From: Xueming Li <xuemingl@nvidia.com>
To: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Cc: Xueming Li <xuemingl@nvidia.com>,
	Edwin Brossette <edwin.brossette@6wind.com>,
	Dariusz Sosnowski <dsosnowski@nvidia.com>,
	"dpdk stable" <stable@dpdk.org>
Subject: patch 'net/mlx5: fix maximal queue size query' has been queued to stable release 23.11.5
Date: Thu, 26 Jun 2025 20:00:46 +0800	[thread overview]
Message-ID: <20250626120145.27369-27-xuemingl@nvidia.com> (raw)
In-Reply-To: <20250626120145.27369-1-xuemingl@nvidia.com>

Hi,

FYI, your patch has been queued to stable release 23.11.5

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 06/28/25. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://git.dpdk.org/dpdk-stable/log/?h=23.11-staging

This queued commit can be viewed at:
https://git.dpdk.org/dpdk-stable/commit/?h=23.11-staging&id=101a72d85868860c46e834db4c91a1a6f7d42749

Thanks.

Xueming Li <xuemingl@nvidia.com>

---
From 101a72d85868860c46e834db4c91a1a6f7d42749 Mon Sep 17 00:00:00 2001
From: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Date: Wed, 14 May 2025 10:55:30 +0300
Subject: [PATCH] net/mlx5: fix maximal queue size query
Cc: Xueming Li <xuemingl@nvidia.com>

[ upstream commit 9de8acd30d5adfc5b9703d15a3e1babc7d4ddacc ]

The mlx5 PMD manages the device using two modes: the Verbs API
and the DevX API. Each API offers its own method for querying
the maximum work queue size (in descriptors).

The corrected patch enhanced the rte_eth_dev_info_get() API
support in mlx5 PMD to return the true maximum number of descriptors.
It also implemented a limit check during queue creation, but this
was applied only to "DevX mode." Consequently, the "Verbs mode"
was overlooked, leading to malfunction on legacy NICs that do
not support DevX.

This patch adds support for Verbs mode, and all limit checks are
updated accordingly.

Fixes: 4c3d7961d900 ("net/mlx5: fix reported Rx/Tx descriptor limits")

Reported-by: Edwin Brossette <edwin.brossette@6wind.com>
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
---
 drivers/common/mlx5/mlx5_prm.h  |  1 +
 drivers/net/mlx5/mlx5.h         |  1 +
 drivers/net/mlx5/mlx5_devx.c    |  2 +-
 drivers/net/mlx5/mlx5_ethdev.c  | 39 +++++++++++++++++++++++++++++----
 drivers/net/mlx5/mlx5_rxq.c     |  2 +-
 drivers/net/mlx5/mlx5_trigger.c |  4 ++--
 drivers/net/mlx5/mlx5_txq.c     | 12 +++++-----
 7 files changed, 47 insertions(+), 14 deletions(-)

diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 79533ff35a..d9e216b635 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -41,6 +41,7 @@
 /* Hardware index widths. */
 #define MLX5_CQ_INDEX_WIDTH 24
 #define MLX5_WQ_INDEX_WIDTH 16
+#define MLX5_WQ_INDEX_MAX (1u << (MLX5_WQ_INDEX_WIDTH - 1))
 
 /* WQE Segment sizes in bytes. */
 #define MLX5_WSEG_SIZE 16u
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index a9129bf61b..75b822785b 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -2122,6 +2122,7 @@ int mlx5_representor_info_get(struct rte_eth_dev *dev,
 		(((repr_id) >> 12) & 3)
 uint16_t mlx5_representor_id_encode(const struct mlx5_switch_info *info,
 				    enum rte_eth_representor_type hpf_type);
+uint16_t mlx5_dev_get_max_wq_size(struct mlx5_dev_ctx_shared *sh);
 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c
index 4f08ddf899..3f8fb9512b 100644
--- a/drivers/net/mlx5/mlx5_devx.c
+++ b/drivers/net/mlx5/mlx5_devx.c
@@ -1527,7 +1527,7 @@ mlx5_txq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx)
 	wqe_size = RTE_ALIGN(wqe_size, MLX5_WQE_SIZE) / MLX5_WQE_SIZE;
 	/* Create Send Queue object with DevX. */
 	wqe_n = RTE_MIN((1UL << txq_data->elts_n) * wqe_size,
-			(uint32_t)priv->sh->dev_cap.max_qp_wr);
+			(uint32_t)mlx5_dev_get_max_wq_size(priv->sh));
 	log_desc_n = log2above(wqe_n);
 	ret = mlx5_txq_create_devx_sq_resources(dev, idx, log_desc_n);
 	if (ret) {
diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c
index 8f29e58cda..4218aef032 100644
--- a/drivers/net/mlx5/mlx5_ethdev.c
+++ b/drivers/net/mlx5/mlx5_ethdev.c
@@ -306,6 +306,37 @@ mlx5_set_txlimit_params(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
 	info->tx_desc_lim.nb_mtu_seg_max = nb_max;
 }
 
+/**
+ * Get maximal work queue size in WQEs
+ *
+ * @param sh
+ *   Pointer to the device shared context.
+ * @return
+ *   Maximal number of WQEs in queue
+ */
+uint16_t
+mlx5_dev_get_max_wq_size(struct mlx5_dev_ctx_shared *sh)
+{
+	uint16_t max_wqe = MLX5_WQ_INDEX_MAX;
+
+	if (sh->cdev->config.devx) {
+		/* use HCA properties for DevX config */
+		MLX5_ASSERT(sh->cdev->config.hca_attr.log_max_wq_sz != 0);
+		MLX5_ASSERT(sh->cdev->config.hca_attr.log_max_wq_sz < MLX5_WQ_INDEX_WIDTH);
+		if (sh->cdev->config.hca_attr.log_max_wq_sz != 0 &&
+		    sh->cdev->config.hca_attr.log_max_wq_sz < MLX5_WQ_INDEX_WIDTH)
+			max_wqe = 1u << sh->cdev->config.hca_attr.log_max_wq_sz;
+	} else {
+		/* use IB device capabilities */
+		MLX5_ASSERT(sh->dev_cap.max_qp_wr > 0);
+		MLX5_ASSERT((unsigned int)sh->dev_cap.max_qp_wr <= MLX5_WQ_INDEX_MAX);
+		if (sh->dev_cap.max_qp_wr > 0 &&
+		    (uint32_t)sh->dev_cap.max_qp_wr <= MLX5_WQ_INDEX_MAX)
+			max_wqe = (uint16_t)sh->dev_cap.max_qp_wr;
+	}
+	return max_wqe;
+}
+
 /**
  * DPDK callback to get information about the device.
  *
@@ -319,6 +350,7 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
 {
 	struct mlx5_priv *priv = dev->data->dev_private;
 	unsigned int max;
+	uint16_t max_wqe;
 
 	/* FIXME: we should ask the device for these values. */
 	info->min_rx_bufsize = 32;
@@ -351,10 +383,9 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
 	info->flow_type_rss_offloads = ~MLX5_RSS_HF_MASK;
 	mlx5_set_default_params(dev, info);
 	mlx5_set_txlimit_params(dev, info);
-	info->rx_desc_lim.nb_max =
-		1 << priv->sh->cdev->config.hca_attr.log_max_wq_sz;
-	info->tx_desc_lim.nb_max =
-		1 << priv->sh->cdev->config.hca_attr.log_max_wq_sz;
+	max_wqe = mlx5_dev_get_max_wq_size(priv->sh);
+	info->rx_desc_lim.nb_max = max_wqe;
+	info->tx_desc_lim.nb_max = max_wqe;
 	if (priv->sh->cdev->config.hca_attr.mem_rq_rmp &&
 	    priv->obj_ops.rxq_obj_new == devx_obj_ops.rxq_obj_new)
 		info->dev_capa |= RTE_ETH_DEV_CAPA_RXQ_SHARE;
diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c
index 7b377974d3..aa8e9316af 100644
--- a/drivers/net/mlx5/mlx5_rxq.c
+++ b/drivers/net/mlx5/mlx5_rxq.c
@@ -655,7 +655,7 @@ mlx5_rx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t *desc,
 	struct mlx5_rxq_priv *rxq;
 	bool empty;
 
-	if (*desc > 1 << priv->sh->cdev->config.hca_attr.log_max_wq_sz) {
+	if (*desc > mlx5_dev_get_max_wq_size(priv->sh)) {
 		DRV_LOG(ERR,
 			"port %u number of descriptors requested for Rx queue"
 			" %u is more than supported",
diff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c
index a4887a8d20..a61128ec21 100644
--- a/drivers/net/mlx5/mlx5_trigger.c
+++ b/drivers/net/mlx5/mlx5_trigger.c
@@ -215,8 +215,8 @@ mlx5_rxq_start(struct rte_eth_dev *dev)
 		/* Should not release Rx queues but return immediately. */
 		return -rte_errno;
 	}
-	DRV_LOG(DEBUG, "Port %u dev_cap.max_qp_wr is %d.",
-		dev->data->port_id, priv->sh->dev_cap.max_qp_wr);
+	DRV_LOG(DEBUG, "Port %u max work queue size is %d.",
+		dev->data->port_id, mlx5_dev_get_max_wq_size(priv->sh));
 	DRV_LOG(DEBUG, "Port %u dev_cap.max_sge is %d.",
 		dev->data->port_id, priv->sh->dev_cap.max_sge);
 	for (i = 0; i != priv->rxqs_n; ++i) {
diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c
index 52a39ae073..0905570f1a 100644
--- a/drivers/net/mlx5/mlx5_txq.c
+++ b/drivers/net/mlx5/mlx5_txq.c
@@ -332,7 +332,7 @@ mlx5_tx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t *desc)
 {
 	struct mlx5_priv *priv = dev->data->dev_private;
 
-	if (*desc > 1 << priv->sh->cdev->config.hca_attr.log_max_wq_sz) {
+	if (*desc > mlx5_dev_get_max_wq_size(priv->sh)) {
 		DRV_LOG(ERR,
 			"port %u number of descriptors requested for Tx queue"
 			" %u is more than supported",
@@ -726,7 +726,7 @@ txq_calc_inline_max(struct mlx5_txq_ctrl *txq_ctrl)
 	struct mlx5_priv *priv = txq_ctrl->priv;
 	unsigned int wqe_size;
 
-	wqe_size = priv->sh->dev_cap.max_qp_wr / desc;
+	wqe_size = mlx5_dev_get_max_wq_size(priv->sh) / desc;
 	if (!wqe_size)
 		return 0;
 	/*
@@ -1081,6 +1081,7 @@ mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
 {
 	struct mlx5_priv *priv = dev->data->dev_private;
 	struct mlx5_txq_ctrl *tmpl;
+	uint16_t max_wqe;
 
 	tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl) +
 			   desc * sizeof(struct rte_mbuf *), 0, socket);
@@ -1106,13 +1107,12 @@ mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
 	txq_set_params(tmpl);
 	if (txq_adjust_params(tmpl))
 		goto error;
-	if (txq_calc_wqebb_cnt(tmpl) >
-	    priv->sh->dev_cap.max_qp_wr) {
+	max_wqe = mlx5_dev_get_max_wq_size(priv->sh);
+	if (txq_calc_wqebb_cnt(tmpl) > max_wqe) {
 		DRV_LOG(ERR,
 			"port %u Tx WQEBB count (%d) exceeds the limit (%d),"
 			" try smaller queue size",
-			dev->data->port_id, txq_calc_wqebb_cnt(tmpl),
-			priv->sh->dev_cap.max_qp_wr);
+			dev->data->port_id, txq_calc_wqebb_cnt(tmpl), max_wqe);
 		rte_errno = ENOMEM;
 		goto error;
 	}
-- 
2.34.1

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2025-06-26 19:59:18.980412677 +0800
+++ 0026-net-mlx5-fix-maximal-queue-size-query.patch	2025-06-26 19:59:17.302418047 +0800
@@ -1 +1 @@
-From 9de8acd30d5adfc5b9703d15a3e1babc7d4ddacc Mon Sep 17 00:00:00 2001
+From 101a72d85868860c46e834db4c91a1a6f7d42749 Mon Sep 17 00:00:00 2001
@@ -4,0 +5,3 @@
+Cc: Xueming Li <xuemingl@nvidia.com>
+
+[ upstream commit 9de8acd30d5adfc5b9703d15a3e1babc7d4ddacc ]
@@ -21 +23,0 @@
-Cc: stable@dpdk.org
@@ -37 +39 @@
-index 742c274a85..7accdeab87 100644
+index 79533ff35a..d9e216b635 100644
@@ -49 +51 @@
-index 36f11b9c51..5695d0f54a 100644
+index a9129bf61b..75b822785b 100644
@@ -52 +54 @@
-@@ -2303,6 +2303,7 @@ int mlx5_representor_info_get(struct rte_eth_dev *dev,
+@@ -2122,6 +2122,7 @@ int mlx5_representor_info_get(struct rte_eth_dev *dev,
@@ -59 +61 @@
- const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev,
+ const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
@@ -61 +63 @@
-index a12891a983..9711746edb 100644
+index 4f08ddf899..3f8fb9512b 100644
@@ -64 +66 @@
-@@ -1593,7 +1593,7 @@ mlx5_txq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx)
+@@ -1527,7 +1527,7 @@ mlx5_txq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx)
@@ -74 +76 @@
-index 7708a0b808..a50320075c 100644
+index 8f29e58cda..4218aef032 100644
@@ -77 +79 @@
-@@ -314,6 +314,37 @@ mlx5_set_txlimit_params(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
+@@ -306,6 +306,37 @@ mlx5_set_txlimit_params(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
@@ -115 +117 @@
-@@ -327,6 +358,7 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
+@@ -319,6 +350,7 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
@@ -123 +125 @@
-@@ -359,10 +391,9 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
+@@ -351,10 +383,9 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
@@ -138 +140 @@
-index ab29b43875..b676e5394b 100644
+index 7b377974d3..aa8e9316af 100644
@@ -141 +143 @@
-@@ -656,7 +656,7 @@ mlx5_rx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t *desc,
+@@ -655,7 +655,7 @@ mlx5_rx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t *desc,
@@ -151 +153 @@
-index 4ee44e9165..8145ad4233 100644
+index a4887a8d20..a61128ec21 100644
@@ -154 +156 @@
-@@ -217,8 +217,8 @@ mlx5_rxq_start(struct rte_eth_dev *dev)
+@@ -215,8 +215,8 @@ mlx5_rxq_start(struct rte_eth_dev *dev)
@@ -166 +168 @@
-index ddd3a66282..5fee5bc4e8 100644
+index 52a39ae073..0905570f1a 100644
@@ -169 +171 @@
-@@ -334,7 +334,7 @@ mlx5_tx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t *desc)
+@@ -332,7 +332,7 @@ mlx5_tx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t *desc)
@@ -178 +180 @@
-@@ -728,7 +728,7 @@ txq_calc_inline_max(struct mlx5_txq_ctrl *txq_ctrl)
+@@ -726,7 +726,7 @@ txq_calc_inline_max(struct mlx5_txq_ctrl *txq_ctrl)
@@ -187 +189 @@
-@@ -1054,6 +1054,7 @@ mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
+@@ -1081,6 +1081,7 @@ mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
@@ -195,2 +197 @@
-@@ -1078,13 +1079,12 @@ mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
- 	tmpl->txq.idx = idx;
+@@ -1106,13 +1107,12 @@ mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
@@ -198 +199,2 @@
- 	txq_adjust_params(tmpl);
+ 	if (txq_adjust_params(tmpl))
+ 		goto error;

  parent reply	other threads:[~2025-06-26 12:04 UTC|newest]

Thread overview: 86+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-26 12:00 patch " Xueming Li
2025-06-26 12:00 ` patch 'ethdev: convert string initialization' " Xueming Li
2025-06-26 12:00 ` patch 'net/fm10k/base: fix compilation warnings' " Xueming Li
2025-06-26 12:00 ` patch 'net/ixgbe/base: correct definition of endianness macro' " Xueming Li
2025-06-26 12:00 ` patch 'net/ixgbe/base: fix compilation warnings' " Xueming Li
2025-06-26 12:00 ` patch 'net/i40e/base: fix unused value " Xueming Li
2025-06-26 12:00 ` patch 'net/i40e/base: fix compiler " Xueming Li
2025-06-26 12:00 ` patch 'acl: fix build with GCC 15 on aarch64' " Xueming Li
2025-06-26 12:00 ` patch 'eal/linux: improve ASLR check' " Xueming Li
2025-06-26 12:00 ` patch 'net/e1000: fix xstats name' " Xueming Li
2025-06-26 12:00 ` patch 'net/e1000: fix EEPROM dump' " Xueming Li
2025-06-26 12:00 ` patch 'net/ixgbe: enable ethertype filter for E610' " Xueming Li
2025-06-26 12:00 ` patch 'net/ixgbe: fix port mask default value in filter' " Xueming Li
2025-06-26 12:00 ` patch 'net/e1000: fix igb Tx queue offloads capability' " Xueming Li
2025-06-26 12:00 ` patch 'net/ice: fix flow creation failure' " Xueming Li
2025-06-26 12:00 ` patch 'vhost: fix wrapping on control virtqueue rings' " Xueming Li
2025-06-26 12:00 ` patch 'vhost/crypto: fix cipher data length' " Xueming Li
2025-06-26 12:00 ` patch 'crypto/virtio: fix cipher data source " Xueming Li
2025-06-26 12:00 ` patch 'app/crypto-perf: fix AAD offset alignment' " Xueming Li
2025-06-26 12:00 ` patch 'crypto/qat: fix out-of-place header bytes in AEAD raw API' " Xueming Li
2025-06-26 12:00 ` patch 'crypto/qat: fix out-of-place chain/cipher/auth headers' " Xueming Li
2025-06-26 12:00 ` patch 'net/mlx5: fix header modify action on group 0' " Xueming Li
2025-06-26 12:00 ` patch 'net/mlx5: validate GTP PSC QFI width' " Xueming Li
2025-06-26 12:00 ` patch 'net/mlx5: fix counter service cleanup on init failure' " Xueming Li
2025-06-26 12:00 ` patch 'net/mlx5/hws: fix send queue drain on FW WQE destroy' " Xueming Li
2025-06-26 12:00 ` patch 'net/mlx5: remove unsupported flow meter action in HWS' " Xueming Li
2025-06-26 12:00 ` Xueming Li [this message]
2025-06-26 12:00 ` patch 'net/mlx5: fix mark action with shared Rx queue' " Xueming Li
2025-06-26 12:00 ` patch 'net/mlx5: align PF and VF/SF MAC address handling' " Xueming Li
2025-06-26 12:00 ` patch 'net/sfc: fix action order on start failure' " Xueming Li
2025-06-26 12:00 ` patch 'net/nfp: fix crash with null RSS hash key' " Xueming Li
2025-06-26 12:00 ` patch 'net/nfp: fix hash key length logic' " Xueming Li
2025-06-26 12:00 ` patch 'app/testpmd: fix RSS hash key update' " Xueming Li
2025-06-26 12:00 ` patch 'net/af_xdp: fix use after free in zero-copy Tx' " Xueming Li
2025-06-26 12:00 ` patch 'net/hns3: fix integer overflow in interrupt unmap' " Xueming Li
2025-06-26 12:00 ` patch 'net/hns3: fix memory leak on failure' " Xueming Li
2025-06-26 12:00 ` patch 'net/hns3: fix extra wait for link up' " Xueming Li
2025-06-26 12:00 ` patch 'net/hns3: fix memory leak for indirect flow action' " Xueming Li
2025-06-26 12:00 ` patch 'net/hns3: fix interrupt rollback' " Xueming Li
2025-06-26 12:00 ` patch 'net/hns3: fix divide by zero' " Xueming Li
2025-06-26 12:01 ` patch 'net/hns3: fix resources release on reset' " Xueming Li
2025-06-26 12:01 ` patch 'net/nfp: standardize NFD3 Tx descriptor endianness' " Xueming Li
2025-06-26 12:01 ` patch 'net/nfp: standardize NFDk " Xueming Li
2025-06-26 12:01 ` patch 'net/qede: fix use after free' " Xueming Li
2025-06-26 12:01 ` patch 'bus/fslmc: " Xueming Li
2025-06-26 12:01 ` patch 'net/null: fix packet copy' " Xueming Li
2025-06-26 12:01 ` patch 'bus/vmbus: align ring buffer data to page boundary' " Xueming Li
2025-06-26 12:01 ` patch 'bus/vmbus: use Hyper-V page size' " Xueming Li
2025-06-26 12:01 ` patch 'net/netvsc: " Xueming Li
2025-06-26 12:01 ` patch 'net/netvsc: add stats counters from VF' " Xueming Li
2025-06-26 12:01 ` patch 'app/testpmd: relax number of TCs in DCB command' " Xueming Li
2025-06-26 12:01 ` patch 'net/mana: check vendor ID when probing RDMA device' " Xueming Li
2025-06-26 12:01 ` patch 'net/hns3: fix CRC data segment' " Xueming Li
2025-06-26 12:01 ` patch 'net/tap: fix qdisc add failure handling' " Xueming Li
2025-06-26 12:01 ` patch 'net/mlx5: fix VLAN stripping on hairpin queue' " Xueming Li
2025-06-26 12:01 ` patch 'mem: fix lockup on address space shortage' " Xueming Li
2025-06-26 12:01 ` patch 'test/malloc: improve resiliency' " Xueming Li
2025-06-26 12:01 ` patch 'trace: fix overflow in per-lcore trace buffer' " Xueming Li
2025-06-26 12:01 ` patch 'common/cnxk: fix E-tag pattern parsing' " Xueming Li
2025-06-26 12:01 ` patch 'common/cnxk: fix CQ tail drop' " Xueming Li
2025-06-26 12:01 ` patch 'net/cnxk: fix descriptor count update on reconfig' " Xueming Li
2025-06-26 12:01 ` patch 'ethdev: fix error struct in flow configure' " Xueming Li
2025-06-26 12:01 ` patch 'net/ice/base: fix integer overflow' " Xueming Li
2025-06-26 12:01 ` patch 'net/ice/base: fix typo in device ID description' " Xueming Li
2025-06-26 12:01 ` patch 'common/dpaax: fix PDCP key command race condition' " Xueming Li
2025-06-26 12:01 ` patch 'common/dpaax: fix PDCP AES only 12-bit SN' " Xueming Li
2025-06-26 12:01 ` patch 'crypto/dpaa2_sec: fix uninitialized variable' " Xueming Li
2025-06-26 12:01 ` patch 'crypto/virtio: add request check on request side' " Xueming Li
2025-06-26 12:01 ` patch 'crypto/virtio: fix driver cleanup' " Xueming Li
2025-06-26 12:01 ` patch 'crypto/virtio: fix driver ID' " Xueming Li
2025-06-26 12:01 ` patch 'ethdev: keep promiscuous/allmulti value before disabling' " Xueming Li
2025-06-26 12:01 ` patch 'eal: fix return value of lcore role' " Xueming Li
2025-06-26 12:01 ` patch 'eal: warn if no lcore is available' " Xueming Li
2025-06-26 12:01 ` patch 'test/lcore: fix race in per-lcore test' " Xueming Li
2025-06-26 12:01 ` patch 'bus: cleanup device lists' " Xueming Li
2025-06-26 12:01 ` patch 'eal/linux: unregister alarm callback before free' " Xueming Li
2025-06-26 12:01 ` patch 'eal/freebsd: " Xueming Li
2025-06-26 12:01 ` patch 'bus/pci/bsd: fix device existence check' " Xueming Li
2025-06-26 12:01 ` patch 'power/intel_uncore: fix crash closing uninitialized driver' " Xueming Li
2025-06-26 12:01 ` patch 'crypto/qat: fix size calculation for memset' " Xueming Li
2025-06-26 12:01 ` patch 'net/mlx5: avoid setting kernel MTU if not needed' " Xueming Li
2025-06-26 12:01 ` patch 'doc: add kernel options required for mlx5' " Xueming Li
2025-06-26 12:01 ` patch 'net/mlx5: fix hypervisor detection in VLAN workaround' " Xueming Li
2025-06-26 12:01 ` patch 'net/hns3: check requirement for hardware GRO' " Xueming Li
2025-06-26 12:01 ` patch 'net/hns3: allow Tx vector when fast free not enabled' " Xueming Li
2025-06-26 12:01 ` patch 'net/hns3: allow Rx vector mode with VLAN filter' " Xueming Li

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