From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0398C46A63 for ; Thu, 26 Jun 2025 14:02:58 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F21DC4028D; Thu, 26 Jun 2025 14:02:57 +0200 (CEST) Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2059.outbound.protection.outlook.com [40.107.244.59]) by mails.dpdk.org (Postfix) with ESMTP id 49926400D6 for ; Thu, 26 Jun 2025 14:02:55 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=L/5z+IPqwUr6iuRAz1B0WnrPhD26d+csS/53ErCmGNTZUMr8BwjGh5JPgv71zUUaTQlMDcUTR8hW8ReLNxmIRv4N/JBUhXazZam2KbU0KwLAuKOb7lvJT+O8bW0qaYrtAMweEBBqz1YA8cKJqCQ5wOXXRe79mmYlBcHWvu6nCiSz1s1/lBxk7hcDEl219OyZRHz/D+afolU1+JG5yVL+PO8h8SlcMrFY1FnJ9yiMdkSU3O7QRnYgVCHeQPHPm9yIL6ZAnsL3WuAjtCFGWflEfhZsy4ZwjWBcrRZScTXLfUQx2omdhFyAYV45DI6j4egbaU0abcUqkN0CpYtTGM1tag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=MIkR2cL2tC/YFXgAF5l/hUXAqYjxl/3vkgRoVgjEosw=; b=qAPK1NZ9I1vaKSA3IjoBfkey8st7N/EZJaVxBrVBOPpg3TNTl12PP8FBnST/aoWbdVU817eWq+n38ycPjHCi2IC+BfOPzIMlczBi3ylf8eL5IW/OBcr+tWT4WuY2w7EfA3n8vrIkQm9m3WeKO89PPholjsH+EysjsvXFB2hi06xKd/G/7BQfiFBzpKO7N/xQGW6eCi3qWdoR3M8NmAYSAhB+8bJLeubk5g71L/Jp6P0mR259nJCWoZsjCxS8zDdYbgq9fK0n/dSXyymc+sErBWYRKNy3sSVo4hF2zZwtXCMkZZY92nxQqYXphZwvR3+S+1VzvZDuoZCjPjUv5juHEQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=redhat.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=MIkR2cL2tC/YFXgAF5l/hUXAqYjxl/3vkgRoVgjEosw=; b=SH9ha6jgxnOEuIWHT2WG3kJzz41GSZ09bD/2Kxm37XLRkj3zzKYzNFiZvxpyoQAkt4DwkfQpOHcDbhkKuk90S9FUgD7Q3ogL5mp/qf38uGsLNtW3P0KZmydagQbdwQp1pTY3pz24P9dkRAEBbpdcg0jSn2PHBApa6pGHHoZdyPpm95/QvLNoN0CrzjnacEdbpDOoHHopWKUACWlDjJRft4DC2ssLx66HZi5sDtBqdlGJowsmMPZ7/mDE7VPxbkip/kRM7BrBsd8CWxw8KwPdP6pW3H/gsRuhg2etU1TYI7xBQbQRplDeGQHc4j2YzxaTNNW3OGOVySXoVO/oklhUbw== Received: from BL1PR13CA0282.namprd13.prod.outlook.com (2603:10b6:208:2bc::17) by MW4PR12MB7191.namprd12.prod.outlook.com (2603:10b6:303:22d::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8880.17; Thu, 26 Jun 2025 12:02:52 +0000 Received: from MN1PEPF0000F0E2.namprd04.prod.outlook.com (2603:10b6:208:2bc:cafe::5) by BL1PR13CA0282.outlook.office365.com (2603:10b6:208:2bc::17) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8901.9 via Frontend Transport; Thu, 26 Jun 2025 12:02:51 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by MN1PEPF0000F0E2.mail.protection.outlook.com (10.167.242.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8880.14 via Frontend Transport; Thu, 26 Jun 2025 12:02:51 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 26 Jun 2025 05:02:28 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Thu, 26 Jun 2025 05:02:26 -0700 From: Xueming Li To: David Marchand CC: Xueming Li , Konstantin Ananyev , Bruce Richardson , dpdk stable Subject: patch 'acl: fix build with GCC 15 on aarch64' has been queued to stable release 23.11.5 Date: Thu, 26 Jun 2025 20:00:27 +0800 Message-ID: <20250626120145.27369-8-xuemingl@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250626120145.27369-1-xuemingl@nvidia.com> References: <20250626120145.27369-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0E2:EE_|MW4PR12MB7191:EE_ X-MS-Office365-Filtering-Correlation-Id: 69775b5e-2061-460b-1bc6-08ddb4a96050 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|376014|36860700013|1800799024|7053199007; X-Microsoft-Antispam-Message-Info: =?utf-8?B?TGsvbVNOZnVGRis2TEhoRXZBR3poOUNPdVA2VHh5T1lJdFVOMmN3UGl3WGpD?= =?utf-8?B?MFFTbXBBWE45RnJqQjF0U0tZaEZkcjMyczRteVhQV3AwUFRaUHEyNGkvYTBL?= =?utf-8?B?alM2RzA3YkxvN3NBRkMwczE0bG43WmpjWkxvZXNsTHVYb1F5c1lId1hPR1Q4?= =?utf-8?B?Q0hnRFRPTnBLTzdnSTNyNEYzS3R1S3M2QW4wWmtVTitFUnduT0tUTldldElp?= =?utf-8?B?WmtBSXdQOVMwZzkzYTVpUzY5QXlJYVlyaUp1VDJtWXZtR0hRSjZKVTN5a1Q1?= =?utf-8?B?aGg3Z0tMSXNQQlFhdXFvdUYyRHQwdmtJMW9mOUlmSWdqdmlsd3dxL0ZzMm95?= =?utf-8?B?bUhzM0RpdkJmd2RITWZtTXVVN3EzSTBRMDdMVFJyb3FiR04yTUxLd29jeDFF?= =?utf-8?B?MGVkQnE2ckdiRC92em9BVjRvWkxSQ092YzBkd3Z1d1AzbnNlTFo4M3VtOGgw?= =?utf-8?B?eWlFdUtxcFo3RGlVSkJwRElET2g1RUN2cDNyZDBJZnlWUHluTGJPSXlnK3Qz?= =?utf-8?B?dzNmYUl1eDlCL1pCK3doa2dESVdiWm5DMDllcVVZdktManE1UEFtWlBaTEwv?= =?utf-8?B?TEVZbHFOU0FrV1ZlbE1NOC9KOUxuTlIrRVJDa0JtRTkxa3EzWGxDM2QyZUdj?= =?utf-8?B?NUpRcXEyYVZXS2YrMjdvT0tnQ0wwbWVCM3BGZG1KNnJiSW1Mb1JaNGE5RENC?= =?utf-8?B?RmVzOVArY3FqbnFOeDJZcitDU3JnNHJQb2hKV3hURXlzdzJyd1Jib1QzN1pP?= =?utf-8?B?czQrZjVycE9VSnN6c2xjUGlUWTdWd3R4MmFuYW12VldSNEQrWmtCV0JnSEs2?= =?utf-8?B?OGNZZzlmQ2UwRmdIcE9mT1ZJdVlzWjhPVnAzUmhxaXlsMFZqWkxwNndjOTJS?= =?utf-8?B?aHFFaVc5N0haNUQwTlBhMVJrbTF4MHkyREl3VlJXUDd0UllrMlNqUkFpMHU0?= =?utf-8?B?bWwyZjQxRHozblgwU1VaZ0JraTRwSnJXY1VSRTBJRmxGOGdmL0gxSVpVQ2s2?= =?utf-8?B?S1pmb0xvUVRSSTFjUmFHbS9KR2ZLVmtMdmZqT0JNRHo1TnZYUy9JS3JpM3Mx?= =?utf-8?B?d0xWREhrRjI3dzhqRDdTdDJFazBucmtMbzJRVExVZFhkVk82THZYV0krMysr?= =?utf-8?B?RlNBOVdMTXVrbFllQTVxb044UEZoMGd4aG5qdzlINHRHRDQzRWNyOFdQWXZQ?= =?utf-8?B?bGt3czRIcmM1YkdTSFF3L3VyVysvZmlJRjkyK2VvWldzZThBZGNCNndRS1ZX?= =?utf-8?B?amRlSHZJVzRsYmZxRzdDcUx2YzEweTJPSFVtWTJHNXVtYTVHWWJER3RCMnVq?= =?utf-8?B?NGF0SXYvc3RjWGU3K3gvdjhRdEZqRHZQSDNJWm1reE4rQXpXS3hrQTY4dmJ0?= =?utf-8?B?MjVHaWk1bm9wWEthaWlZdnpuaXF3S3R6TG03NHJCTGhSYXltb1JFa1gyYW1E?= =?utf-8?B?VVQrNWhnVThkNE9ZV01JajdLakwrMjR4NDVVd3FSQlVMYnlxemh2SWxiMjZo?= =?utf-8?B?WHNabUVMcG9PZ09jU0hFVFY2MnpnaG9OQnRvOWZjS2FzVzROWGdBaGFWeWY1?= =?utf-8?B?eTRxaFdjSGNyMFk2aSsrc2s3KzltbDVraDVBWmRWb1VnVzJXTWZwcDdXOXM2?= =?utf-8?B?TmlBNFhsVmgxeUVBMWs1M1FZRGFHTlpzT2RxeTNwSERJdFNhYzA1SGZzTmpI?= =?utf-8?B?dW92NVRjeDJwL3pIQ2dZaDlwNWgwM1NGcStrci91dmNVZFRaaisvVk16eVlj?= =?utf-8?B?UlltbTJqSk9OcTd0SlA1UlZyRTUwSkQ4UWpHb1FKeXBMTEM4N3dQcFR2WU4v?= =?utf-8?B?c1ZHY2RiRDhwa2xuaVgwVmxqQlhsbkhXTmhQanVuOW9mMDd6Q244QW1VdVlT?= =?utf-8?B?bFZsMnZ6a0ExMjJ5b1BXR2txdEJPc3YvR0U3aHFvdXFuOFN4eUF2NVdaenRi?= =?utf-8?B?ZHFPWHN4WUhTeFVFSTFveUJRNXlQMjlYNlhHUFdoNXdmYTVUUGNXdUdPeStt?= =?utf-8?B?RWtGZVBIdEl2TjBMYWpjMEJ6ZnJBUmRHSzByVlN5THcrVE53c1FvR1ZaUG16?= =?utf-8?B?SC8xL2FXS3lFQ1hFL1cvNlNnQjlJczJuTGVlQT09?= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(376014)(36860700013)(1800799024)(7053199007); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2025 12:02:51.2895 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 69775b5e-2061-460b-1bc6-08ddb4a96050 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E2.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7191 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 23.11.5 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 06/28/25. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://git.dpdk.org/dpdk-stable/log/?h=23.11-staging This queued commit can be viewed at: https://git.dpdk.org/dpdk-stable/commit/?h=23.11-staging&id=794bc328016be580bce9bae57b4ffe12ef0e1a6f Thanks. Xueming Li --- >From 794bc328016be580bce9bae57b4ffe12ef0e1a6f Mon Sep 17 00:00:00 2001 From: David Marchand Date: Wed, 26 Mar 2025 11:29:02 +0100 Subject: [PATCH] acl: fix build with GCC 15 on aarch64 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Xueming Li [ upstream commit 6cde8a3dda49ad2721ac15faedf1965cdb4980b0 ] Caught in OBS for Fedora Rawhide on aarch64: [ 198s] In file included from ../lib/acl/acl_run_neon.h:7, [ 198s] from ../lib/acl/acl_run_neon.c:5: [ 198s] In function ‘alloc_completion’, [ 198s] inlined from ‘acl_start_next_trie’ at ../lib/acl/acl_run.h:140:24, [ 198s] inlined from ‘search_neon_4.isra’ at ../lib/acl/acl_run_neon.h:239:20: [ 198s] ../lib/acl/acl_run.h:93:25: error: ‘cmplt’ may be used uninitialized [-Werror=maybe-uninitialized] [ 198s] 93 | if (p[n].count == 0) { [ 198s] | ~~~~^~~~~~ [ 198s] ../lib/acl/acl_run_neon.h: In function ‘search_neon_4.isra’: [ 198s] ../lib/acl/acl_run_neon.h:230:27: note: ‘cmplt’ declared here [ 198s] 230 | struct completion cmplt[4]; [ 198s] | ^~~~~ The code was resetting sequentially cmpl[].count at the exact index that later call to alloc_completion uses. While this code seems correct, GCC 15 does not understand this (probably when applying some optimisations). Instead, reset cmpl[].count all at once in acl_set_flow, and cleanup the various vectorized implementations accordingly. Bugzilla ID: 1678 Signed-off-by: David Marchand Acked-by: Konstantin Ananyev Tested-by: Konstantin Ananyev Acked-by: Bruce Richardson --- lib/acl/acl_run.h | 5 +++++ lib/acl/acl_run_altivec.h | 8 ++------ lib/acl/acl_run_avx2.h | 4 +--- lib/acl/acl_run_neon.h | 8 ++------ lib/acl/acl_run_scalar.c | 4 +--- lib/acl/acl_run_sse.h | 8 ++------ 6 files changed, 13 insertions(+), 24 deletions(-) diff --git a/lib/acl/acl_run.h b/lib/acl/acl_run.h index 7d215de9d6..533f233f68 100644 --- a/lib/acl/acl_run.h +++ b/lib/acl/acl_run.h @@ -176,6 +176,8 @@ acl_set_flow(struct acl_flow_data *flows, struct completion *cmplt, uint32_t cmplt_size, const uint8_t **data, uint32_t *results, uint32_t data_num, uint32_t categories, const uint64_t *trans) { + unsigned int i; + flows->num_packets = 0; flows->started = 0; flows->trie = 0; @@ -187,6 +189,9 @@ acl_set_flow(struct acl_flow_data *flows, struct completion *cmplt, flows->data = data; flows->results = results; flows->trans = trans; + + for (i = 0; i < cmplt_size; i++) + cmplt[i].count = 0; } typedef void (*resolve_priority_t) diff --git a/lib/acl/acl_run_altivec.h b/lib/acl/acl_run_altivec.h index 3c30466d2d..c38727eab0 100644 --- a/lib/acl/acl_run_altivec.h +++ b/lib/acl/acl_run_altivec.h @@ -197,10 +197,8 @@ search_altivec_8(const struct rte_acl_ctx *ctx, const uint8_t **data, acl_set_flow(&flows, cmplt, RTE_DIM(cmplt), data, results, total_packets, categories, ctx->trans_table); - for (n = 0; n < MAX_SEARCHES_ALTIVEC8; n++) { - cmplt[n].count = 0; + for (n = 0; n < MAX_SEARCHES_ALTIVEC8; n++) index_array[n] = acl_start_next_trie(&flows, parms, n, ctx); - } /* Check for any matches. */ acl_match_check_x4(0, ctx, parms, &flows, (uint64_t *)&index_array[0]); @@ -268,10 +266,8 @@ search_altivec_4(const struct rte_acl_ctx *ctx, const uint8_t **data, acl_set_flow(&flows, cmplt, RTE_DIM(cmplt), data, results, total_packets, categories, ctx->trans_table); - for (n = 0; n < MAX_SEARCHES_ALTIVEC4; n++) { - cmplt[n].count = 0; + for (n = 0; n < MAX_SEARCHES_ALTIVEC4; n++) index_array[n] = acl_start_next_trie(&flows, parms, n, ctx); - } /* Check for any matches. */ acl_match_check_x4(0, ctx, parms, &flows, index_array); diff --git a/lib/acl/acl_run_avx2.h b/lib/acl/acl_run_avx2.h index 0b8967f22e..e069fb85b2 100644 --- a/lib/acl/acl_run_avx2.h +++ b/lib/acl/acl_run_avx2.h @@ -171,10 +171,8 @@ search_avx2x16(const struct rte_acl_ctx *ctx, const uint8_t **data, acl_set_flow(&flows, cmplt, RTE_DIM(cmplt), data, results, total_packets, categories, ctx->trans_table); - for (n = 0; n < RTE_DIM(cmplt); n++) { - cmplt[n].count = 0; + for (n = 0; n < RTE_DIM(cmplt); n++) index_array[n] = acl_start_next_trie(&flows, parms, n, ctx); - } t0 = _mm256_set_epi64x(index_array[5], index_array[4], index_array[1], index_array[0]); diff --git a/lib/acl/acl_run_neon.h b/lib/acl/acl_run_neon.h index 69d1b6d9e1..e31d56e7d0 100644 --- a/lib/acl/acl_run_neon.h +++ b/lib/acl/acl_run_neon.h @@ -170,10 +170,8 @@ search_neon_8(const struct rte_acl_ctx *ctx, const uint8_t **data, acl_set_flow(&flows, cmplt, RTE_DIM(cmplt), data, results, total_packets, categories, ctx->trans_table); - for (n = 0; n < 8; n++) { - cmplt[n].count = 0; + for (n = 0; n < 8; n++) index_array[n] = acl_start_next_trie(&flows, parms, n, ctx); - } /* Check for any matches. */ acl_match_check_x4(0, ctx, parms, &flows, &index_array[0]); @@ -232,10 +230,8 @@ search_neon_4(const struct rte_acl_ctx *ctx, const uint8_t **data, acl_set_flow(&flows, cmplt, RTE_DIM(cmplt), data, results, total_packets, categories, ctx->trans_table); - for (n = 0; n < 4; n++) { - cmplt[n].count = 0; + for (n = 0; n < 4; n++) index_array[n] = acl_start_next_trie(&flows, parms, n, ctx); - } /* Check for any matches. */ acl_match_check_x4(0, ctx, parms, &flows, index_array); diff --git a/lib/acl/acl_run_scalar.c b/lib/acl/acl_run_scalar.c index 3d61e79409..a3661b1b6b 100644 --- a/lib/acl/acl_run_scalar.c +++ b/lib/acl/acl_run_scalar.c @@ -121,10 +121,8 @@ rte_acl_classify_scalar(const struct rte_acl_ctx *ctx, const uint8_t **data, acl_set_flow(&flows, cmplt, RTE_DIM(cmplt), data, results, num, categories, ctx->trans_table); - for (n = 0; n < MAX_SEARCHES_SCALAR; n++) { - cmplt[n].count = 0; + for (n = 0; n < MAX_SEARCHES_SCALAR; n++) index_array[n] = acl_start_next_trie(&flows, parms, n, ctx); - } transition0 = index_array[0]; transition1 = index_array[1]; diff --git a/lib/acl/acl_run_sse.h b/lib/acl/acl_run_sse.h index 93286a2c38..4ec819a215 100644 --- a/lib/acl/acl_run_sse.h +++ b/lib/acl/acl_run_sse.h @@ -205,10 +205,8 @@ search_sse_8(const struct rte_acl_ctx *ctx, const uint8_t **data, acl_set_flow(&flows, cmplt, RTE_DIM(cmplt), data, results, total_packets, categories, ctx->trans_table); - for (n = 0; n < MAX_SEARCHES_SSE8; n++) { - cmplt[n].count = 0; + for (n = 0; n < MAX_SEARCHES_SSE8; n++) index_array[n] = acl_start_next_trie(&flows, parms, n, ctx); - } /* * indices1 contains index_array[0,1] @@ -293,10 +291,8 @@ search_sse_4(const struct rte_acl_ctx *ctx, const uint8_t **data, acl_set_flow(&flows, cmplt, RTE_DIM(cmplt), data, results, total_packets, categories, ctx->trans_table); - for (n = 0; n < MAX_SEARCHES_SSE4; n++) { - cmplt[n].count = 0; + for (n = 0; n < MAX_SEARCHES_SSE4; n++) index_array[n] = acl_start_next_trie(&flows, parms, n, ctx); - } indices1 = _mm_loadu_si128((xmm_t *) &index_array[0]); indices2 = _mm_loadu_si128((xmm_t *) &index_array[2]); -- 2.34.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2025-06-26 19:59:18.045704916 +0800 +++ 0007-acl-fix-build-with-GCC-15-on-aarch64.patch 2025-06-26 19:59:17.186418052 +0800 @@ -1 +1 @@ -From 6cde8a3dda49ad2721ac15faedf1965cdb4980b0 Mon Sep 17 00:00:00 2001 +From 794bc328016be580bce9bae57b4ffe12ef0e1a6f Mon Sep 17 00:00:00 2001 @@ -7,0 +8,3 @@ +Cc: Xueming Li + +[ upstream commit 6cde8a3dda49ad2721ac15faedf1965cdb4980b0 ] @@ -36 +38,0 @@ -Cc: stable@dpdk.org @@ -52 +54 @@ -index 7f092413cd..9fd3e60021 100644 +index 7d215de9d6..533f233f68 100644 @@ -75 +77 @@ -index 2d398ffded..d5ccdb94f0 100644 +index 3c30466d2d..c38727eab0 100644 @@ -78 +80 @@ -@@ -199,10 +199,8 @@ search_altivec_8(const struct rte_acl_ctx *ctx, const uint8_t **data, +@@ -197,10 +197,8 @@ search_altivec_8(const struct rte_acl_ctx *ctx, const uint8_t **data, @@ -90 +92 @@ -@@ -270,10 +268,8 @@ search_altivec_4(const struct rte_acl_ctx *ctx, const uint8_t **data, +@@ -268,10 +266,8 @@ search_altivec_4(const struct rte_acl_ctx *ctx, const uint8_t **data, @@ -119 +121 @@ -index 63074f871d..3b9bd0cc39 100644 +index 69d1b6d9e1..e31d56e7d0 100644 @@ -122 +124 @@ -@@ -172,10 +172,8 @@ search_neon_8(const struct rte_acl_ctx *ctx, const uint8_t **data, +@@ -170,10 +170,8 @@ search_neon_8(const struct rte_acl_ctx *ctx, const uint8_t **data, @@ -134 +136 @@ -@@ -234,10 +232,8 @@ search_neon_4(const struct rte_acl_ctx *ctx, const uint8_t **data, +@@ -232,10 +230,8 @@ search_neon_4(const struct rte_acl_ctx *ctx, const uint8_t **data, @@ -147 +149 @@ -index 8ffb40776c..32ebe3119b 100644 +index 3d61e79409..a3661b1b6b 100644 @@ -150 +152 @@ -@@ -124,10 +124,8 @@ rte_acl_classify_scalar(const struct rte_acl_ctx *ctx, const uint8_t **data, +@@ -121,10 +121,8 @@ rte_acl_classify_scalar(const struct rte_acl_ctx *ctx, const uint8_t **data,