patches for DPDK stable branches
 help / color / mirror / Atom feed
From: luca.boccassi@gmail.com
To: Praveen Kaligineedi <pkaligineedi@google.com>
Cc: Joshua Washington <joshwash@google.com>, dpdk stable <stable@dpdk.org>
Subject: patch 'net/gve: allocate Rx QPL pages using malloc' has been queued to stable release 22.11.11
Date: Mon, 27 Oct 2025 16:18:39 +0000	[thread overview]
Message-ID: <20251027162001.3710450-1-luca.boccassi@gmail.com> (raw)

Hi,

FYI, your patch has been queued to stable release 22.11.11

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 10/29/25. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://github.com/bluca/dpdk-stable

This queued commit can be viewed at:
https://github.com/bluca/dpdk-stable/commit/1d1ce9c3bf042be1763e2164ab6427f2d674a590

Thanks.

Luca Boccassi

---
From 1d1ce9c3bf042be1763e2164ab6427f2d674a590 Mon Sep 17 00:00:00 2001
From: Praveen Kaligineedi <pkaligineedi@google.com>
Date: Thu, 4 Sep 2025 13:59:32 -0700
Subject: [PATCH] net/gve: allocate Rx QPL pages using malloc

Allocating QPL for an RX queue might fail if enough contiguous IOVA
memory cannot be allocated. This can commonly occur when using 2MB huge
pages because the 1024 4K buffers are allocated for each RX ring by
default, resulting in 4MB for each ring. However, the only requirement
for RX QPLs is that each 4K buffer be IOVA contiguous, not the entire
QPL. Therefore, malloc will be used to allocate RX QPLs instead.

Note that TX queues require the entire QPL to be IOVA contiguous, so it
will continue to use the memzone-based allocation.

Fixes: a46583cf43c8 ("net/gve: support Rx/Tx")

Signed-off-by: Praveen Kaligineedi <pkaligineedi@google.com>
Signed-off-by: Joshua Washington <joshwash@google.com>
---
 drivers/net/gve/gve_ethdev.c | 142 +++++++++++++++++++++++++++++------
 drivers/net/gve/gve_ethdev.h |   5 +-
 drivers/net/gve/gve_rx.c     |   4 +-
 3 files changed, 126 insertions(+), 25 deletions(-)

diff --git a/drivers/net/gve/gve_ethdev.c b/drivers/net/gve/gve_ethdev.c
index 0796d37760..43b2b8b2b0 100644
--- a/drivers/net/gve/gve_ethdev.c
+++ b/drivers/net/gve/gve_ethdev.c
@@ -28,13 +28,45 @@ gve_write_version(uint8_t *driver_version_register)
 	writeb('\n', driver_version_register);
 }
 
+static const struct rte_memzone *
+gve_alloc_using_mz(const char *name, uint32_t num_pages)
+{
+	const struct rte_memzone *mz;
+	mz = rte_memzone_reserve_aligned(name, num_pages * PAGE_SIZE,
+					 rte_socket_id(),
+					 RTE_MEMZONE_IOVA_CONTIG, PAGE_SIZE);
+	if (mz == NULL)
+		PMD_DRV_LOG(ERR, "Failed to alloc memzone %s.", name);
+	return mz;
+}
+
+static int
+gve_alloc_using_malloc(void **bufs, uint32_t num_entries)
+{
+	uint32_t i;
+
+	for (i = 0; i < num_entries; i++) {
+		bufs[i] = rte_malloc_socket(NULL, PAGE_SIZE, PAGE_SIZE, rte_socket_id());
+		if (bufs[i] == NULL) {
+			PMD_DRV_LOG(ERR, "Failed to malloc");
+			goto free_bufs;
+		}
+	}
+	return 0;
+
+free_bufs:
+	while (i > 0)
+		rte_free(bufs[--i]);
+
+	return -ENOMEM;
+}
+
 static int
-gve_alloc_queue_page_list(struct gve_priv *priv, uint32_t id, uint32_t pages)
+gve_alloc_queue_page_list(struct gve_priv *priv, uint32_t id, uint32_t pages,
+			  bool is_rx)
 {
-	char z_name[RTE_MEMZONE_NAMESIZE];
 	struct gve_queue_page_list *qpl;
-	const struct rte_memzone *mz;
-	dma_addr_t page_bus;
+	int err = 0;
 	uint32_t i;
 
 	if (priv->num_registered_pages + pages >
@@ -45,31 +77,79 @@ gve_alloc_queue_page_list(struct gve_priv *priv, uint32_t id, uint32_t pages)
 		return -EINVAL;
 	}
 	qpl = &priv->qpl[id];
-	snprintf(z_name, sizeof(z_name), "gve_%s_qpl%d", priv->pci_dev->device.name, id);
-	mz = rte_memzone_reserve_aligned(z_name, pages * PAGE_SIZE,
-					 rte_socket_id(),
-					 RTE_MEMZONE_IOVA_CONTIG, PAGE_SIZE);
-	if (mz == NULL) {
-		PMD_DRV_LOG(ERR, "Failed to alloc %s.", z_name);
-		return -ENOMEM;
-	}
+
 	qpl->page_buses = rte_zmalloc("qpl page buses", pages * sizeof(dma_addr_t), 0);
 	if (qpl->page_buses == NULL) {
 		PMD_DRV_LOG(ERR, "Failed to alloc qpl %u page buses", id);
 		return -ENOMEM;
 	}
-	page_bus = mz->iova;
-	for (i = 0; i < pages; i++) {
-		qpl->page_buses[i] = page_bus;
-		page_bus += PAGE_SIZE;
+
+	if (is_rx) {
+		/* RX QPL need not be IOVA contiguous.
+		 * Allocate 4K size buffers using malloc
+		 */
+		qpl->qpl_bufs = rte_zmalloc("qpl bufs",
+			pages * sizeof(void *), 0);
+		if (qpl->qpl_bufs == NULL) {
+			PMD_DRV_LOG(ERR, "Failed to alloc qpl bufs");
+			err = -ENOMEM;
+			goto free_qpl_page_buses;
+		}
+
+		err = gve_alloc_using_malloc(qpl->qpl_bufs, pages);
+		if (err)
+			goto free_qpl_page_bufs;
+
+		/* Populate the IOVA addresses */
+		for (i = 0; i < pages; i++)
+			qpl->page_buses[i] =
+				rte_malloc_virt2iova(qpl->qpl_bufs[i]);
+	} else {
+		char z_name[RTE_MEMZONE_NAMESIZE];
+
+		snprintf(z_name, sizeof(z_name), "gve_%s_qpl%d", priv->pci_dev->device.name, id);
+
+		/* TX QPL needs to be IOVA contiguous
+		 * Allocate QPL using memzone
+		 */
+		qpl->mz = gve_alloc_using_mz(z_name, pages);
+		if (!qpl->mz) {
+			err = -ENOMEM;
+			goto free_qpl_page_buses;
+		}
+
+		/* Populate the IOVA addresses */
+		for (i = 0; i < pages; i++)
+			qpl->page_buses[i] = qpl->mz->iova + i * PAGE_SIZE;
 	}
+
 	qpl->id = id;
-	qpl->mz = mz;
 	qpl->num_entries = pages;
 
 	priv->num_registered_pages += pages;
 
 	return 0;
+
+free_qpl_page_bufs:
+	rte_free(qpl->qpl_bufs);
+free_qpl_page_buses:
+	rte_free(qpl->page_buses);
+	return err;
+}
+
+/*
+ * Free QPL bufs in RX QPLs. Should not be used on TX QPLs.
+ **/
+static void
+gve_free_qpl_bufs(struct gve_queue_page_list *qpl)
+{
+	uint32_t i;
+
+	for (i = 0; i < qpl->num_entries; i++)
+		rte_free(qpl->qpl_bufs[i]);
+
+	rte_free(qpl->qpl_bufs);
+	qpl->qpl_bufs = NULL;
 }
 
 static void
@@ -79,9 +159,22 @@ gve_free_qpls(struct gve_priv *priv)
 	uint16_t nb_rxqs = priv->max_nb_rxq;
 	uint32_t i;
 
-	for (i = 0; i < nb_txqs + nb_rxqs; i++) {
-		if (priv->qpl[i].mz != NULL)
+	if (priv->queue_format != GVE_GQI_QPL_FORMAT)
+		return;
+
+	/* Free TX QPLs. */
+	for (i = 0; i < nb_txqs; i++) {
+		if (priv->qpl[i].mz) {
 			rte_memzone_free(priv->qpl[i].mz);
+			priv->qpl[i].mz = NULL;
+		}
+		rte_free(priv->qpl[i].page_buses);
+	}
+
+	/* Free RX QPLs. */
+	for (; i < nb_rxqs; i++) {
+		if (priv->qpl[i].qpl_bufs)
+			gve_free_qpl_bufs(&priv->qpl[i]);
 		rte_free(priv->qpl[i].page_buses);
 	}
 
@@ -562,11 +655,16 @@ gve_init_priv(struct gve_priv *priv, bool skip_describe_device)
 		}
 
 		for (i = 0; i < priv->max_nb_txq + priv->max_nb_rxq; i++) {
-			if (i < priv->max_nb_txq)
+			bool is_rx;
+
+			if (i < priv->max_nb_txq) {
 				pages = priv->tx_pages_per_qpl;
-			else
+				is_rx = false;
+			} else {
 				pages = priv->rx_data_slot_cnt;
-			err = gve_alloc_queue_page_list(priv, i, pages);
+				is_rx = true;
+			}
+			err = gve_alloc_queue_page_list(priv, i, pages, is_rx);
 			if (err != 0) {
 				PMD_DRV_LOG(ERR, "Failed to alloc qpl %u.", i);
 				goto err_qpl;
diff --git a/drivers/net/gve/gve_ethdev.h b/drivers/net/gve/gve_ethdev.h
index b7702a1249..effacc2795 100644
--- a/drivers/net/gve/gve_ethdev.h
+++ b/drivers/net/gve/gve_ethdev.h
@@ -39,7 +39,10 @@ struct gve_queue_page_list {
 	uint32_t id; /* unique id */
 	uint32_t num_entries;
 	dma_addr_t *page_buses; /* the dma addrs of the pages */
-	const struct rte_memzone *mz;
+	union {
+		const struct rte_memzone *mz; /* memzone allocated for TX queue */
+		void **qpl_bufs; /* RX qpl-buffer list allocated using malloc*/
+	};
 };
 
 /* A TX desc ring entry */
diff --git a/drivers/net/gve/gve_rx.c b/drivers/net/gve/gve_rx.c
index 50f9f5c370..e020b4af10 100644
--- a/drivers/net/gve/gve_rx.c
+++ b/drivers/net/gve/gve_rx.c
@@ -105,9 +105,9 @@ gve_rx_burst(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 		len = rte_be_to_cpu_16(rxd->len) - GVE_RX_PAD;
 		rxe = rxq->sw_ring[rx_id];
 		if (rxq->is_gqi_qpl) {
-			addr = (uint64_t)(rxq->qpl->mz->addr) + rx_id * PAGE_SIZE + GVE_RX_PAD;
+			addr = (uint64_t)rxq->qpl->qpl_bufs[rx_id] + GVE_RX_PAD;
 			rte_memcpy((void *)((size_t)rxe->buf_addr + rxe->data_off),
-				   (void *)(size_t)addr, len);
+					    (void *)(size_t)addr, len);
 		}
 		rxe->pkt_len = len;
 		rxe->data_len = len;
-- 
2.47.3


             reply	other threads:[~2025-10-27 16:20 UTC|newest]

Thread overview: 79+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-27 16:18 luca.boccassi [this message]
2025-10-27 16:18 ` patch 'eal: fix plugin dir walk' " luca.boccassi
2025-10-27 16:18 ` patch 'cmdline: fix port list parsing' " luca.boccassi
2025-10-27 16:18 ` patch 'cmdline: fix highest bit " luca.boccassi
2025-10-27 16:18 ` patch 'tailq: fix lookup macro' " luca.boccassi
2025-10-27 16:18 ` patch 'hash: fix unaligned access in predictable RSS' " luca.boccassi
2025-10-27 16:18 ` patch 'graph: fix unaligned access in stats' " luca.boccassi
2025-10-27 16:18 ` patch 'eventdev: fix listing timer adapters with telemetry' " luca.boccassi
2025-10-27 16:18 ` patch 'cfgfile: fix section count with no name' " luca.boccassi
2025-10-27 16:18 ` patch 'net/vmxnet3: fix mapping of mempools to queues' " luca.boccassi
2025-10-27 16:18 ` patch 'app/testpmd: increase size of set cores list command' " luca.boccassi
2025-10-27 16:18 ` patch 'net/dpaa2: fix shaper rate' " luca.boccassi
2025-10-27 16:18 ` patch 'app/testpmd: monitor state of primary process' " luca.boccassi
2025-10-27 16:18 ` patch 'app/testpmd: fix conntrack action query' " luca.boccassi
2025-10-27 16:18 ` patch 'doc: add conntrack state inspect command to testpmd guide' " luca.boccassi
2025-10-27 16:18 ` patch 'app/testpmd: validate DSCP and VLAN for meter creation' " luca.boccassi
2025-10-27 16:18 ` patch 'net/mlx5: fix min and max MTU reporting' " luca.boccassi
2025-10-27 16:18 ` patch 'net/mlx5: fix unsupported flow rule port action' " luca.boccassi
2025-10-27 16:18 ` patch 'net/mlx5: fix non-template age rules flush' " luca.boccassi
2025-10-27 16:18 ` patch 'net/mlx5: fix connection tracking state item validation' " luca.boccassi
2025-10-27 16:18 ` patch 'net/mlx5: fix indirect flow age action handling' " luca.boccassi
2025-10-27 16:19 ` patch 'net/mlx5: fix Direct Verbs counter offset detection' " luca.boccassi
2025-10-27 16:19 ` patch 'net/mlx5: fix interface name parameter definition' " luca.boccassi
2025-10-27 16:19 ` patch 'net/intel: fix assumption about tag placement order' " luca.boccassi
2025-10-27 16:19 ` patch 'net/ice/base: fix adding special words' " luca.boccassi
2025-10-27 16:19 ` patch 'net/ice/base: fix memory leak in HW profile handling' " luca.boccassi
2025-10-27 16:19 ` patch 'net/ice/base: fix memory leak in recipe " luca.boccassi
2025-10-27 16:19 ` patch 'eal: fix DMA mask validation with IOVA mode option' " luca.boccassi
2025-10-27 16:19 ` patch 'eal: fix MP socket cleanup' " luca.boccassi
2025-10-27 16:19 ` patch 'crypto/ipsec_mb: fix QP release in secondary' " luca.boccassi
2025-10-27 16:19 ` patch 'efd: fix AVX2 support' " luca.boccassi
2025-10-27 16:19 ` patch 'common/cnxk: fix async event handling' " luca.boccassi
2025-10-27 16:19 ` patch 'doc: fix feature list of ice driver' " luca.boccassi
2025-10-27 16:19 ` patch 'doc: fix feature list of iavf " luca.boccassi
2025-10-27 16:19 ` patch 'baseband/acc: fix exported header' " luca.boccassi
2025-10-27 16:19 ` patch 'gpudev: fix driver header for Windows' " luca.boccassi
2025-10-27 16:19 ` patch 'drivers: fix some exported headers' " luca.boccassi
2025-10-27 16:19 ` patch 'test/debug: fix crash with mlx5 devices' " luca.boccassi
2025-10-27 16:19 ` patch 'bus/pci: fix build with MinGW 13' " luca.boccassi
2025-10-27 16:19 ` patch 'net/mlx5: " luca.boccassi
2025-10-27 16:19 ` patch 'dma/hisilicon: fix stop with pending transfers' " luca.boccassi
2025-10-27 16:19 ` patch 'test/dma: fix failure condition' " luca.boccassi
2025-10-27 16:19 ` patch 'fib6: fix tbl8 allocation check logic' " luca.boccassi
2025-10-27 16:19 ` patch 'vhost: fix double fetch when dequeue offloading' " luca.boccassi
2025-10-27 16:19 ` patch 'net/ice/base: fix integer overflow on NVM init' " luca.boccassi
2025-10-27 16:19 ` patch 'net/ice: fix initialization with 8 ports' " luca.boccassi
2025-10-27 16:19 ` patch 'net/ice: remove indirection for FDIR filters' " luca.boccassi
2025-10-27 16:19 ` patch 'net/ice: fix memory leak in raw pattern parse' " luca.boccassi
2025-10-27 16:19 ` patch 'net/i40e: fix symmetric Toeplitz hashing for SCTP' " luca.boccassi
2025-10-27 16:19 ` patch 'net/mlx5: fix multicast' " luca.boccassi
2025-10-27 16:19 ` patch 'net/mlx5: fix MTU initialization' " luca.boccassi
2025-10-27 16:19 ` patch 'net/mlx5: fix leak of flow indexed pools' " luca.boccassi
2025-10-27 16:19 ` patch 'net/hns3: fix inconsistent lock' " luca.boccassi
2025-10-27 16:19 ` patch 'net/hns3: fix VLAN resources freeing' " luca.boccassi
2025-10-27 16:19 ` patch 'net/af_packet: fix crash in secondary process' " luca.boccassi
2025-10-27 16:19 ` patch 'net/ark: remove double mbuf free' " luca.boccassi
2025-10-27 16:19 ` patch 'net/hns3: fix VLAN tag loss for short tunnel frame' " luca.boccassi
2025-10-27 16:19 ` patch 'ethdev: fix VLAN filter parameter description' " luca.boccassi
2025-10-27 16:19 ` patch 'net/enetfec: fix file descriptor leak on read error' " luca.boccassi
2025-10-27 16:19 ` patch 'net/enetfec: fix out-of-bounds access in UIO mapping' " luca.boccassi
2025-10-27 16:19 ` patch 'net/enetfec: fix buffer descriptor size configuration' " luca.boccassi
2025-10-27 16:19 ` patch 'net/enetfec: fix Tx queue free' " luca.boccassi
2025-10-27 16:19 ` patch 'net/enetfec: fix checksum flag handling and error return' " luca.boccassi
2025-10-27 16:19 ` patch 'net/enetfec: reject multi-queue configuration' " luca.boccassi
2025-10-27 16:19 ` patch 'net/enetfec: fix memory leak in Rx buffer cleanup' " luca.boccassi
2025-10-27 16:19 ` patch 'net/enetfec: reject Tx deferred queue' " luca.boccassi
2025-10-27 16:19 ` patch 'net/tap: fix interrupt callback crash after failed start' " luca.boccassi
2025-10-27 16:19 ` patch 'net/ena: fix PCI BAR mapping on 64K page size' " luca.boccassi
2025-10-27 16:19 ` patch 'net/ena/base: fix unsafe memcpy on invalid memory' " luca.boccassi
2025-10-27 16:19 ` patch 'net/dpaa2: fix uninitialized variable' " luca.boccassi
2025-10-27 16:19 ` patch 'net/dpaa2: fix L3/L4 checksum results' " luca.boccassi
2025-10-27 16:19 ` patch 'net/dpaa2: receive packets with additional parse errors' " luca.boccassi
2025-10-27 16:19 ` patch 'crypto/qat: fix source buffer alignment' " luca.boccassi
2025-10-27 16:19 ` patch 'crypto/cnxk: refactor RSA verification' " luca.boccassi
2025-10-27 16:19 ` patch 'test/crypto: fix mbuf handling' " luca.boccassi
2025-10-27 16:19 ` patch 'app/crypto-perf: fix plaintext size exceeds buffer size' " luca.boccassi
2025-10-27 16:19 ` patch 'test/crypto: fix vector initialization' " luca.boccassi
2025-10-27 16:19 ` patch 'crypto/virtio: fix cookies leak' " luca.boccassi
2025-10-27 16:19 ` patch 'sched: fix WRR parameter data type' " luca.boccassi

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20251027162001.3710450-1-luca.boccassi@gmail.com \
    --to=luca.boccassi@gmail.com \
    --cc=joshwash@google.com \
    --cc=pkaligineedi@google.com \
    --cc=stable@dpdk.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).