patches for DPDK stable branches
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From: luca.boccassi@gmail.com
To: Chengwen Feng <fengchengwen@huawei.com>
Cc: dpdk stable <stable@dpdk.org>
Subject: patch 'dma/hisilicon: fix stop with pending transfers' has been queued to stable release 22.11.11
Date: Mon, 27 Oct 2025 16:19:19 +0000	[thread overview]
Message-ID: <20251027162001.3710450-41-luca.boccassi@gmail.com> (raw)
In-Reply-To: <20251027162001.3710450-1-luca.boccassi@gmail.com>

Hi,

FYI, your patch has been queued to stable release 22.11.11

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 10/29/25. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://github.com/bluca/dpdk-stable

This queued commit can be viewed at:
https://github.com/bluca/dpdk-stable/commit/ff8d762481472039fe6f3001c83468f7c97bf9e9

Thanks.

Luca Boccassi

---
From ff8d762481472039fe6f3001c83468f7c97bf9e9 Mon Sep 17 00:00:00 2001
From: Chengwen Feng <fengchengwen@huawei.com>
Date: Mon, 13 Oct 2025 17:22:11 +0800
Subject: [PATCH] dma/hisilicon: fix stop with pending transfers

[ upstream commit 8aa458f1c44b9f6e73f75047aca77191dc79746f ]

Stop dmadev may fail if there are pending DMA transfers, we need make
sure there are no pending DMA transfers when stop.

This commit uses following scheme:
1. flag stop proc so that new request will not process.
2. setting drop flag for all descriptor to quick complete.
3. waiting dmadev to complete.

Fixes: 3c5f5f03a047 ("dma/hisilicon: add control path")

Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
---
 drivers/dma/hisilicon/hisi_dmadev.c | 45 ++++++++++++++++++++++++-----
 drivers/dma/hisilicon/hisi_dmadev.h |  2 ++
 2 files changed, 39 insertions(+), 8 deletions(-)

diff --git a/drivers/dma/hisilicon/hisi_dmadev.c b/drivers/dma/hisilicon/hisi_dmadev.c
index 4db3b0554c..29aed3e156 100644
--- a/drivers/dma/hisilicon/hisi_dmadev.c
+++ b/drivers/dma/hisilicon/hisi_dmadev.c
@@ -378,6 +378,7 @@ hisi_dma_start(struct rte_dma_dev *dev)
 	hw->cq_head = 0;
 	hw->cqs_completed = 0;
 	hw->cqe_vld = 1;
+	hw->stop_proc = 0;
 	hw->submitted = 0;
 	hw->completed = 0;
 	hw->errors = 0;
@@ -389,12 +390,6 @@ hisi_dma_start(struct rte_dma_dev *dev)
 	return 0;
 }
 
-static int
-hisi_dma_stop(struct rte_dma_dev *dev)
-{
-	return hisi_dma_reset_hw(dev->data->dev_private);
-}
-
 static int
 hisi_dma_close(struct rte_dma_dev *dev)
 {
@@ -456,6 +451,37 @@ hisi_dma_vchan_status(const struct rte_dma_dev *dev, uint16_t vchan,
 	return 0;
 }
 
+static int
+hisi_dma_stop(struct rte_dma_dev *dev)
+{
+#define MAX_WAIT_MSEC	10
+	struct hisi_dma_dev *hw = dev->data->dev_private;
+	enum rte_dma_vchan_status status;
+	uint32_t i;
+
+	/* Flag stop processing new requests. */
+	hw->stop_proc = 1;
+	rte_delay_ms(1);
+
+	/* Force set drop flag so that the hardware can quickly complete. */
+	for (i = 0; i <= hw->sq_depth_mask; i++)
+		hw->sqe[i].dw0 |= SQE_DROP_FLAG;
+
+	i = 0;
+	do {
+		hisi_dma_vchan_status(dev, 0, &status);
+		if (status != RTE_DMA_VCHAN_ACTIVE)
+			break;
+		rte_delay_ms(1);
+	} while (i++ < MAX_WAIT_MSEC);
+	if (status == RTE_DMA_VCHAN_ACTIVE) {
+		HISI_DMA_ERR(hw, "dev is still active!");
+		return -EBUSY;
+	}
+
+	return hisi_dma_reset_hw(dev->data->dev_private);
+}
+
 static void
 hisi_dma_dump_range(struct hisi_dma_dev *hw, FILE *f, uint32_t start,
 		    uint32_t end)
@@ -550,14 +576,14 @@ hisi_dma_dump(const struct rte_dma_dev *dev, FILE *f)
 		"    revision: 0x%x queue_id: %u ring_size: %u\n"
 		"    ridx: %u cridx: %u\n"
 		"    sq_head: %u sq_tail: %u cq_sq_head: %u\n"
-		"    cq_head: %u cqs_completed: %u cqe_vld: %u\n"
+		"    cq_head: %u cqs_completed: %u cqe_vld: %u stop_proc: %u\n"
 		"    submitted: %" PRIu64 " completed: %" PRIu64 " errors: %"
 		PRIu64 " qfulls: %" PRIu64 "\n",
 		hw->revision, hw->queue_id,
 		hw->sq_depth_mask > 0 ? hw->sq_depth_mask + 1 : 0,
 		hw->ridx, hw->cridx,
 		hw->sq_head, hw->sq_tail, hw->cq_sq_head,
-		hw->cq_head, hw->cqs_completed, hw->cqe_vld,
+		hw->cq_head, hw->cqs_completed, hw->cqe_vld, hw->stop_proc,
 		hw->submitted, hw->completed, hw->errors, hw->qfulls);
 	hisi_dma_dump_queue(hw, f);
 	hisi_dma_dump_common(hw, f);
@@ -575,6 +601,9 @@ hisi_dma_copy(void *dev_private, uint16_t vchan,
 
 	RTE_SET_USED(vchan);
 
+	if (unlikely(hw->stop_proc > 0))
+		return -EPERM;
+
 	if (((hw->sq_tail + 1) & hw->sq_depth_mask) == hw->sq_head) {
 		hw->qfulls++;
 		return -ENOSPC;
diff --git a/drivers/dma/hisilicon/hisi_dmadev.h b/drivers/dma/hisilicon/hisi_dmadev.h
index a57b5c759a..b9dd172c31 100644
--- a/drivers/dma/hisilicon/hisi_dmadev.h
+++ b/drivers/dma/hisilicon/hisi_dmadev.h
@@ -141,6 +141,7 @@ enum {
 
 struct hisi_dma_sqe {
 	uint32_t dw0;
+#define SQE_DROP_FLAG	BIT(4)
 #define SQE_FENCE_FLAG	BIT(10)
 #define SQE_OPCODE_M2M	0x4
 	uint32_t dw1;
@@ -211,6 +212,7 @@ struct hisi_dma_dev {
 	 */
 	uint16_t cqs_completed;
 	uint8_t cqe_vld; /**< valid bit for CQE, will change for every round. */
+	volatile uint8_t stop_proc; /**< whether stop processing new requests. */
 
 	uint64_t submitted;
 	uint64_t completed;
-- 
2.47.3

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2025-10-27 15:54:36.342690329 +0000
+++ 0041-dma-hisilicon-fix-stop-with-pending-transfers.patch	2025-10-27 15:54:34.811949950 +0000
@@ -1 +1 @@
-From 8aa458f1c44b9f6e73f75047aca77191dc79746f Mon Sep 17 00:00:00 2001
+From ff8d762481472039fe6f3001c83468f7c97bf9e9 Mon Sep 17 00:00:00 2001
@@ -5,0 +6,2 @@
+[ upstream commit 8aa458f1c44b9f6e73f75047aca77191dc79746f ]
+
@@ -15 +16,0 @@
-Cc: stable@dpdk.org
@@ -24 +25 @@
-index 019c4a8189..7575fb12d9 100644
+index 4db3b0554c..29aed3e156 100644
@@ -27 +28 @@
-@@ -376,6 +376,7 @@ hisi_dma_start(struct rte_dma_dev *dev)
+@@ -378,6 +378,7 @@ hisi_dma_start(struct rte_dma_dev *dev)
@@ -35 +36 @@
-@@ -387,12 +388,6 @@ hisi_dma_start(struct rte_dma_dev *dev)
+@@ -389,12 +390,6 @@ hisi_dma_start(struct rte_dma_dev *dev)
@@ -48 +49 @@
-@@ -454,6 +449,37 @@ hisi_dma_vchan_status(const struct rte_dma_dev *dev, uint16_t vchan,
+@@ -456,6 +451,37 @@ hisi_dma_vchan_status(const struct rte_dma_dev *dev, uint16_t vchan,
@@ -86 +87 @@
-@@ -548,14 +574,14 @@ hisi_dma_dump(const struct rte_dma_dev *dev, FILE *f)
+@@ -550,14 +576,14 @@ hisi_dma_dump(const struct rte_dma_dev *dev, FILE *f)
@@ -103 +104 @@
-@@ -573,6 +599,9 @@ hisi_dma_copy(void *dev_private, uint16_t vchan,
+@@ -575,6 +601,9 @@ hisi_dma_copy(void *dev_private, uint16_t vchan,
@@ -114 +115 @@
-index 90301e6b00..aab87c40be 100644
+index a57b5c759a..b9dd172c31 100644

  parent reply	other threads:[~2025-10-27 16:22 UTC|newest]

Thread overview: 79+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-27 16:18 patch 'net/gve: allocate Rx QPL pages using malloc' " luca.boccassi
2025-10-27 16:18 ` patch 'eal: fix plugin dir walk' " luca.boccassi
2025-10-27 16:18 ` patch 'cmdline: fix port list parsing' " luca.boccassi
2025-10-27 16:18 ` patch 'cmdline: fix highest bit " luca.boccassi
2025-10-27 16:18 ` patch 'tailq: fix lookup macro' " luca.boccassi
2025-10-27 16:18 ` patch 'hash: fix unaligned access in predictable RSS' " luca.boccassi
2025-10-27 16:18 ` patch 'graph: fix unaligned access in stats' " luca.boccassi
2025-10-27 16:18 ` patch 'eventdev: fix listing timer adapters with telemetry' " luca.boccassi
2025-10-27 16:18 ` patch 'cfgfile: fix section count with no name' " luca.boccassi
2025-10-27 16:18 ` patch 'net/vmxnet3: fix mapping of mempools to queues' " luca.boccassi
2025-10-27 16:18 ` patch 'app/testpmd: increase size of set cores list command' " luca.boccassi
2025-10-27 16:18 ` patch 'net/dpaa2: fix shaper rate' " luca.boccassi
2025-10-27 16:18 ` patch 'app/testpmd: monitor state of primary process' " luca.boccassi
2025-10-27 16:18 ` patch 'app/testpmd: fix conntrack action query' " luca.boccassi
2025-10-27 16:18 ` patch 'doc: add conntrack state inspect command to testpmd guide' " luca.boccassi
2025-10-27 16:18 ` patch 'app/testpmd: validate DSCP and VLAN for meter creation' " luca.boccassi
2025-10-27 16:18 ` patch 'net/mlx5: fix min and max MTU reporting' " luca.boccassi
2025-10-27 16:18 ` patch 'net/mlx5: fix unsupported flow rule port action' " luca.boccassi
2025-10-27 16:18 ` patch 'net/mlx5: fix non-template age rules flush' " luca.boccassi
2025-10-27 16:18 ` patch 'net/mlx5: fix connection tracking state item validation' " luca.boccassi
2025-10-27 16:18 ` patch 'net/mlx5: fix indirect flow age action handling' " luca.boccassi
2025-10-27 16:19 ` patch 'net/mlx5: fix Direct Verbs counter offset detection' " luca.boccassi
2025-10-27 16:19 ` patch 'net/mlx5: fix interface name parameter definition' " luca.boccassi
2025-10-27 16:19 ` patch 'net/intel: fix assumption about tag placement order' " luca.boccassi
2025-10-27 16:19 ` patch 'net/ice/base: fix adding special words' " luca.boccassi
2025-10-27 16:19 ` patch 'net/ice/base: fix memory leak in HW profile handling' " luca.boccassi
2025-10-27 16:19 ` patch 'net/ice/base: fix memory leak in recipe " luca.boccassi
2025-10-27 16:19 ` patch 'eal: fix DMA mask validation with IOVA mode option' " luca.boccassi
2025-10-27 16:19 ` patch 'eal: fix MP socket cleanup' " luca.boccassi
2025-10-27 16:19 ` patch 'crypto/ipsec_mb: fix QP release in secondary' " luca.boccassi
2025-10-27 16:19 ` patch 'efd: fix AVX2 support' " luca.boccassi
2025-10-27 16:19 ` patch 'common/cnxk: fix async event handling' " luca.boccassi
2025-10-27 16:19 ` patch 'doc: fix feature list of ice driver' " luca.boccassi
2025-10-27 16:19 ` patch 'doc: fix feature list of iavf " luca.boccassi
2025-10-27 16:19 ` patch 'baseband/acc: fix exported header' " luca.boccassi
2025-10-27 16:19 ` patch 'gpudev: fix driver header for Windows' " luca.boccassi
2025-10-27 16:19 ` patch 'drivers: fix some exported headers' " luca.boccassi
2025-10-27 16:19 ` patch 'test/debug: fix crash with mlx5 devices' " luca.boccassi
2025-10-27 16:19 ` patch 'bus/pci: fix build with MinGW 13' " luca.boccassi
2025-10-27 16:19 ` patch 'net/mlx5: " luca.boccassi
2025-10-27 16:19 ` luca.boccassi [this message]
2025-10-27 16:19 ` patch 'test/dma: fix failure condition' " luca.boccassi
2025-10-27 16:19 ` patch 'fib6: fix tbl8 allocation check logic' " luca.boccassi
2025-10-27 16:19 ` patch 'vhost: fix double fetch when dequeue offloading' " luca.boccassi
2025-10-27 16:19 ` patch 'net/ice/base: fix integer overflow on NVM init' " luca.boccassi
2025-10-27 16:19 ` patch 'net/ice: fix initialization with 8 ports' " luca.boccassi
2025-10-27 16:19 ` patch 'net/ice: remove indirection for FDIR filters' " luca.boccassi
2025-10-27 16:19 ` patch 'net/ice: fix memory leak in raw pattern parse' " luca.boccassi
2025-10-27 16:19 ` patch 'net/i40e: fix symmetric Toeplitz hashing for SCTP' " luca.boccassi
2025-10-27 16:19 ` patch 'net/mlx5: fix multicast' " luca.boccassi
2025-10-27 16:19 ` patch 'net/mlx5: fix MTU initialization' " luca.boccassi
2025-10-27 16:19 ` patch 'net/mlx5: fix leak of flow indexed pools' " luca.boccassi
2025-10-27 16:19 ` patch 'net/hns3: fix inconsistent lock' " luca.boccassi
2025-10-27 16:19 ` patch 'net/hns3: fix VLAN resources freeing' " luca.boccassi
2025-10-27 16:19 ` patch 'net/af_packet: fix crash in secondary process' " luca.boccassi
2025-10-27 16:19 ` patch 'net/ark: remove double mbuf free' " luca.boccassi
2025-10-27 16:19 ` patch 'net/hns3: fix VLAN tag loss for short tunnel frame' " luca.boccassi
2025-10-27 16:19 ` patch 'ethdev: fix VLAN filter parameter description' " luca.boccassi
2025-10-27 16:19 ` patch 'net/enetfec: fix file descriptor leak on read error' " luca.boccassi
2025-10-27 16:19 ` patch 'net/enetfec: fix out-of-bounds access in UIO mapping' " luca.boccassi
2025-10-27 16:19 ` patch 'net/enetfec: fix buffer descriptor size configuration' " luca.boccassi
2025-10-27 16:19 ` patch 'net/enetfec: fix Tx queue free' " luca.boccassi
2025-10-27 16:19 ` patch 'net/enetfec: fix checksum flag handling and error return' " luca.boccassi
2025-10-27 16:19 ` patch 'net/enetfec: reject multi-queue configuration' " luca.boccassi
2025-10-27 16:19 ` patch 'net/enetfec: fix memory leak in Rx buffer cleanup' " luca.boccassi
2025-10-27 16:19 ` patch 'net/enetfec: reject Tx deferred queue' " luca.boccassi
2025-10-27 16:19 ` patch 'net/tap: fix interrupt callback crash after failed start' " luca.boccassi
2025-10-27 16:19 ` patch 'net/ena: fix PCI BAR mapping on 64K page size' " luca.boccassi
2025-10-27 16:19 ` patch 'net/ena/base: fix unsafe memcpy on invalid memory' " luca.boccassi
2025-10-27 16:19 ` patch 'net/dpaa2: fix uninitialized variable' " luca.boccassi
2025-10-27 16:19 ` patch 'net/dpaa2: fix L3/L4 checksum results' " luca.boccassi
2025-10-27 16:19 ` patch 'net/dpaa2: receive packets with additional parse errors' " luca.boccassi
2025-10-27 16:19 ` patch 'crypto/qat: fix source buffer alignment' " luca.boccassi
2025-10-27 16:19 ` patch 'crypto/cnxk: refactor RSA verification' " luca.boccassi
2025-10-27 16:19 ` patch 'test/crypto: fix mbuf handling' " luca.boccassi
2025-10-27 16:19 ` patch 'app/crypto-perf: fix plaintext size exceeds buffer size' " luca.boccassi
2025-10-27 16:19 ` patch 'test/crypto: fix vector initialization' " luca.boccassi
2025-10-27 16:19 ` patch 'crypto/virtio: fix cookies leak' " luca.boccassi
2025-10-27 16:19 ` patch 'sched: fix WRR parameter data type' " luca.boccassi

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