patch 'dma/hisilicon: fix stop with pending transfers' has been queued to stable release 24.11.4

[Kevin Traynor <ktraynor@redhat.com>]

Hi,

FYI, your patch has been queued to stable release 24.11.4

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 11/05/25. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://github.com/kevintraynor/dpdk-stable

This queued commit can be viewed at:
https://github.com/kevintraynor/dpdk-stable/commit/caf6bf8424e73315be792d4759a593509f1d50e6

Thanks.

Kevin

---
From caf6bf8424e73315be792d4759a593509f1d50e6 Mon Sep 17 00:00:00 2001
From: Chengwen Feng <fengchengwen@huawei.com>
Date: Mon, 13 Oct 2025 17:22:11 +0800
Subject: [PATCH] dma/hisilicon: fix stop with pending transfers

[ upstream commit 8aa458f1c44b9f6e73f75047aca77191dc79746f ]

Stop dmadev may fail if there are pending DMA transfers, we need make
sure there are no pending DMA transfers when stop.

This commit uses following scheme:
1. flag stop proc so that new request will not process.
2. setting drop flag for all descriptor to quick complete.
3. waiting dmadev to complete.

Fixes: 3c5f5f03a047 ("dma/hisilicon: add control path")

Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
---
 drivers/dma/hisilicon/hisi_dmadev.c | 45 ++++++++++++++++++++++++-----
 drivers/dma/hisilicon/hisi_dmadev.h |  2 ++
 2 files changed, 39 insertions(+), 8 deletions(-)

diff --git a/drivers/dma/hisilicon/hisi_dmadev.c b/drivers/dma/hisilicon/hisi_dmadev.c
index fdd2fa225f..feac145e29 100644
--- a/drivers/dma/hisilicon/hisi_dmadev.c
+++ b/drivers/dma/hisilicon/hisi_dmadev.c
@@ -377,4 +377,5 @@ hisi_dma_start(struct rte_dma_dev *dev)
 	hw->cqs_completed = 0;
 	hw->cqe_vld = 1;
+	hw->stop_proc = 0;
 	hw->submitted = 0;
 	hw->completed = 0;
@@ -388,10 +389,4 @@ hisi_dma_start(struct rte_dma_dev *dev)
 }
 
-static int
-hisi_dma_stop(struct rte_dma_dev *dev)
-{
-	return hisi_dma_reset_hw(dev->data->dev_private);
-}
-
 static int
 hisi_dma_close(struct rte_dma_dev *dev)
@@ -455,4 +450,35 @@ hisi_dma_vchan_status(const struct rte_dma_dev *dev, uint16_t vchan,
 }
 
+static int
+hisi_dma_stop(struct rte_dma_dev *dev)
+{
+#define MAX_WAIT_MSEC	10
+	struct hisi_dma_dev *hw = dev->data->dev_private;
+	enum rte_dma_vchan_status status;
+	uint32_t i;
+
+	/* Flag stop processing new requests. */
+	hw->stop_proc = 1;
+	rte_delay_ms(1);
+
+	/* Force set drop flag so that the hardware can quickly complete. */
+	for (i = 0; i <= hw->sq_depth_mask; i++)
+		hw->sqe[i].dw0 |= SQE_DROP_FLAG;
+
+	i = 0;
+	do {
+		hisi_dma_vchan_status(dev, 0, &status);
+		if (status != RTE_DMA_VCHAN_ACTIVE)
+			break;
+		rte_delay_ms(1);
+	} while (i++ < MAX_WAIT_MSEC);
+	if (status == RTE_DMA_VCHAN_ACTIVE) {
+		HISI_DMA_ERR(hw, "dev is still active!");
+		return -EBUSY;
+	}
+
+	return hisi_dma_reset_hw(dev->data->dev_private);
+}
+
 static void
 hisi_dma_dump_range(struct hisi_dma_dev *hw, FILE *f, uint32_t start,
@@ -549,5 +575,5 @@ hisi_dma_dump(const struct rte_dma_dev *dev, FILE *f)
 		"    ridx: %u cridx: %u\n"
 		"    sq_head: %u sq_tail: %u cq_sq_head: %u\n"
-		"    cq_head: %u cqs_completed: %u cqe_vld: %u\n"
+		"    cq_head: %u cqs_completed: %u cqe_vld: %u stop_proc: %u\n"
 		"    submitted: %" PRIu64 " completed: %" PRIu64 " errors: %"
 		PRIu64 " qfulls: %" PRIu64 "\n",
@@ -556,5 +582,5 @@ hisi_dma_dump(const struct rte_dma_dev *dev, FILE *f)
 		hw->ridx, hw->cridx,
 		hw->sq_head, hw->sq_tail, hw->cq_sq_head,
-		hw->cq_head, hw->cqs_completed, hw->cqe_vld,
+		hw->cq_head, hw->cqs_completed, hw->cqe_vld, hw->stop_proc,
 		hw->submitted, hw->completed, hw->errors, hw->qfulls);
 	hisi_dma_dump_queue(hw, f);
@@ -574,4 +600,7 @@ hisi_dma_copy(void *dev_private, uint16_t vchan,
 	RTE_SET_USED(vchan);
 
+	if (unlikely(hw->stop_proc > 0))
+		return -EPERM;
+
 	if (((hw->sq_tail + 1) & hw->sq_depth_mask) == hw->sq_head) {
 		hw->qfulls++;
diff --git a/drivers/dma/hisilicon/hisi_dmadev.h b/drivers/dma/hisilicon/hisi_dmadev.h
index 786fe3cc0e..5e3c8debcc 100644
--- a/drivers/dma/hisilicon/hisi_dmadev.h
+++ b/drivers/dma/hisilicon/hisi_dmadev.h
@@ -143,4 +143,5 @@ enum {
 struct hisi_dma_sqe {
 	uint32_t dw0;
+#define SQE_DROP_FLAG	BIT(4)
 #define SQE_FENCE_FLAG	BIT(10)
 #define SQE_OPCODE_M2M	0x4
@@ -213,4 +214,5 @@ struct hisi_dma_dev {
 	uint16_t cqs_completed;
 	uint8_t cqe_vld; /**< valid bit for CQE, will change for every round. */
+	volatile uint8_t stop_proc; /**< whether stop processing new requests. */
 
 	uint64_t submitted;
-- 
2.51.0

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2025-10-31 13:53:54.301364499 +0000
+++ 0067-dma-hisilicon-fix-stop-with-pending-transfers.patch	2025-10-31 13:53:52.172444764 +0000
@@ -1 +1 @@
-From 8aa458f1c44b9f6e73f75047aca77191dc79746f Mon Sep 17 00:00:00 2001
+From caf6bf8424e73315be792d4759a593509f1d50e6 Mon Sep 17 00:00:00 2001
@@ -5,0 +6,2 @@
+[ upstream commit 8aa458f1c44b9f6e73f75047aca77191dc79746f ]
+
@@ -15 +16,0 @@
-Cc: stable@dpdk.org
@@ -24 +25 @@
-index 019c4a8189..7575fb12d9 100644
+index fdd2fa225f..feac145e29 100644
@@ -103 +104 @@
-index 90301e6b00..aab87c40be 100644
+index 786fe3cc0e..5e3c8debcc 100644
@@ -106 +107 @@
-@@ -142,4 +142,5 @@ enum {
+@@ -143,4 +143,5 @@ enum {
@@ -112 +113 @@
-@@ -212,4 +213,5 @@ struct hisi_dma_dev {
+@@ -213,4 +214,5 @@ struct hisi_dma_dev {