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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Nov 2025 04:14:24.4770 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7c8307aa-6fec-48a9-f2f1-08de258fcacd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D7.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV9PR12MB9808 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org The structure definitions of "rte_flow_item_tag" and internal "mlx5_rte_flow_item_tag" are different. The handling of them should be split even in one function. It will check the type and then convert to the proper structure. Fixes: c55c2bf35333 ("net/mlx5/hws: add definer layer") Cc: valex@nvidia.com Cc: stable@dpdk.org Signed-off-by: Bing Zhao --- drivers/net/mlx5/hws/mlx5dr_definer.c | 32 ++++++++++++++++++--------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index afa70bf793..010952eb20 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -213,6 +213,7 @@ struct mlx5dr_definer_conv_data { X(SET, mpls_udp_port, UDP_PORT_MPLS, rte_flow_item_mpls) \ X(SET, source_qp, v->queue, mlx5_rte_flow_item_sq) \ X(SET, tag, v->data, rte_flow_item_tag) \ + X(SET, mlx5_tag, v->data, mlx5_rte_flow_item_tag) \ X(SET, metadata, v->data, rte_flow_item_meta) \ X(SET_BE16, geneve_protocol, v->protocol, rte_flow_item_geneve) \ X(SET, geneve_udp_port, UDP_GENEVE_PORT, rte_flow_item_geneve) \ @@ -1796,22 +1797,26 @@ mlx5dr_definer_conv_item_tag(struct mlx5dr_definer_conv_data *cd, struct rte_flow_item *item, int item_idx) { - const struct rte_flow_item_tag *m = item->mask; - const struct rte_flow_item_tag *v = item->spec; - const struct rte_flow_item_tag *l = item->last; + const struct rte_flow_item_tag *ev; + const struct rte_flow_item_tag *el; + const struct mlx5_rte_flow_item_tag *iv; + const struct mlx5_rte_flow_item_tag *il; struct mlx5dr_definer_fc *fc; int reg; - if (!m || !v) + if (!item->mask || !item->spec) return 0; - if (item->type == RTE_FLOW_ITEM_TYPE_TAG) + if (item->type == RTE_FLOW_ITEM_TYPE_TAG) { + ev = item->spec; reg = flow_hw_get_reg_id_from_ctx(cd->ctx, RTE_FLOW_ITEM_TYPE_TAG, cd->table_type, - v->index); - else - reg = (int)v->index; + ev->index); + } else { + iv = item->spec; + reg = (int)iv->id; + } if (reg <= 0) { DR_LOG(ERR, "Invalid register for item tag"); @@ -1824,8 +1829,15 @@ mlx5dr_definer_conv_item_tag(struct mlx5dr_definer_conv_data *cd, return rte_errno; fc->item_idx = item_idx; - fc->is_range = l && l->index; - fc->tag_set = &mlx5dr_definer_tag_set; + if (item->type == RTE_FLOW_ITEM_TYPE_TAG) { + el = item->last; + fc->is_range = el && el->data; + c->tag_set = &mlx5dr_definer_tag_set; + } else { + il = item->last; + fc->is_range = il && il->data; + fc->tag_set = &mlx5dr_definer_mlx5_tag_set; + } return 0; } -- 2.34.1