From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E0A6748B41 for ; Tue, 18 Nov 2025 17:52:46 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CA3BC4027D; Tue, 18 Nov 2025 17:52:46 +0100 (CET) Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012035.outbound.protection.outlook.com [52.101.43.35]) by mails.dpdk.org (Postfix) with ESMTP id 4AC634027D for ; Tue, 18 Nov 2025 17:52:45 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=pGtwtT8ukHt3vYiOcTWbSx3f8lo+r6cMA5+m3XW+jlaY3YP2muQey7ds4vbwwMsJAz46bferjbb/B2zeJ0dS3NGQNGglqrA+YDy8O9ovqkPZQrZxuPKR1qTh07PH8288bq5w1EvJP4wgZKNKTDFsr5c0i1BaBxJFwd7kqH73QwXuuevn8gV5sea4qMWonLoeqcWFi91JEjs5qPRDDp6AiDOskjyH+KkhdTNwTYY6/jmLkCcrmgM/iljWK6wZXnszxj1ehLnYgONWvkF2LMuhEbb+Iz442YQFAv0IkdWfGXC6zY2zIjKJBLX/1COq9lCfV47kVeuNwYQAoFnJd/sftA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=L4x/BsyfIrXjEgrJ54bKuds4w+kjykwT94iscDBqhSc=; b=ubPJRanCXe1iJV7Jcu85tQUjCcSwkJgENpeqK1VurPhbeB8gR32p7oUyHk0/IdEIRvZ0qNij7TlSL1J5n/TH5a/V6P95qZnHvhiHlcEdzarpR6mzi1xSVSWtZ5RogtjaMtJRWxCEcyoR9NU3W9oisSC3W5Zyk+zmmCHHiaKDF/XbXiDSFhCoqaABTFUTISB9yLj75O68mrYl3pCq/cv1IrNkKx2XhQtsMzxxGuU97LXwv19TWCKrF+VN2S0BGPO8SCnEDdQGccdgZ9iyEInz7+63ewZFtbuj+xIK6HQUypu2rC60Pm4jBnFbp8ED1gYdQlGH58c/VIfk0mOmZQRoEg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=L4x/BsyfIrXjEgrJ54bKuds4w+kjykwT94iscDBqhSc=; b=tzyKnyMMq32HVjsVBsKvFOBczpq14OaEh15HSeMhA+8QyJNgSkNjZ4a4K76CaUaKBmE2fP8ijlhiGPW8ALgWMDa8Syaqpf5qXrurNksHCO3B7rywNRkvq7rJR0LOUXukx8T+qYAIM7ibIzotCx9V45IsOK5zZ/gErmfhDHyVFETWnv3I0RUq8cxa09GPY4QlUCVzGjZXuzmjD+y9l3vmMR6iahwyQ+G2tJIFpbJQphcAQr/IY392LBlCUExDGUgO33ZHOQGZXGOKmxsy7BRohUtZFO/5S4MsZS9hYFOPt5LQcw1CuwQwq0nnJks4+EsViy83b+02YbWFVRetiOJH8g== Received: from CYXPR02CA0052.namprd02.prod.outlook.com (2603:10b6:930:cd::22) by SA1PR12MB7223.namprd12.prod.outlook.com (2603:10b6:806:2bc::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9320.21; Tue, 18 Nov 2025 16:52:38 +0000 Received: from CY4PEPF0000EDD3.namprd03.prod.outlook.com (2603:10b6:930:cd:cafe::fb) by CYXPR02CA0052.outlook.office365.com (2603:10b6:930:cd::22) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9343.10 via Frontend Transport; Tue, 18 Nov 2025 16:52:38 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by CY4PEPF0000EDD3.mail.protection.outlook.com (10.167.241.199) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9343.9 via Frontend Transport; Tue, 18 Nov 2025 16:52:38 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 18 Nov 2025 08:52:15 -0800 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 18 Nov 2025 08:52:13 -0800 From: Viacheslav Ovsiienko To: CC: , , , "Dariusz Sosnowski" Subject: [PATCH 22.11] net/mlx5: fix control flow leakage for external SQ Date: Tue, 18 Nov 2025 18:51:58 +0200 Message-ID: <20251118165158.1315992-1-viacheslavo@nvidia.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD3:EE_|SA1PR12MB7223:EE_ X-MS-Office365-Filtering-Correlation-Id: f8e8d79b-cebf-4e4d-7daf-08de26c2e17e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|1800799024|82310400026|36860700013|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?nT7hnrlwvb8vxC3uBm60ppZcRq9Hw6OOZO6CNLJepuCQwCNWIIrxy7iVZdKb?= =?us-ascii?Q?Df3OKKCIofRXNEa0jO+DqxCBO7cTj3BzDRDsSGgj8TNul7KPRcyv7qgX7unn?= =?us-ascii?Q?U0df+yIvJFyFcb88qQbtEKSFrOQh0jN4OoVjQyV6XdRokws9uQj+VlJdqeE7?= =?us-ascii?Q?KPymHJEpX+y53T06kPPOFltvqMuoHMJVmWzj6rR4OqfevtR38mu4icr7bR70?= =?us-ascii?Q?OsBHrvkp1Bks3IK56QSkx6jExwgrmLKyLtQSLdMFppukAk3RrLNRtwe0pKPA?= =?us-ascii?Q?xYp/lrDaX6OnaRVhs4ssvnZE883ylQT1L8nmRZHLw3xoUslSweRwabmWdsjs?= =?us-ascii?Q?vr48Mbu3Nb15tQCJi/qo4rdauPwmABqP0zAl3Ph8SYjRkWv8DUO2wflJ9Kad?= =?us-ascii?Q?p8MsDaLPJSDYgAJCCyxhR0UwvUrOuRNk/5Y372jkAFH2SfE/bkZ7/Yw6/OuJ?= =?us-ascii?Q?iPKJOTfO3+J63JilUUmb8ADI6A2u9TLgS8Bv1os0BISXMvXfL0S2ebtOlYVA?= =?us-ascii?Q?dqUoIb5s5Xdwjo3X7X4eu7DhM510H3D3BZRxkuosb28LZh5f2/E54ZwHnqpx?= =?us-ascii?Q?C+QfXP/cMV6CWxZu524TAn6kHpg2xa+A7iC25g/dqlkexUVCo4t2l9CYWlMK?= =?us-ascii?Q?0xmrQWa6vZA/Q8ZnEOIR+9J/W/EJjwxVR8Fk4w+s8jjrsdA+llwMohQaO6D0?= =?us-ascii?Q?nDOz4Cq4sKucJM384/Q/BqfDNNb84eqyN12l2hcD+2+YCeJqKj9O6wqlUWQ+?= =?us-ascii?Q?s5TWGdh7MX+rdAhhJJH0AduQ6ZvcYQmwNu2ufJRS/q7/bXeavnmWDIMri312?= =?us-ascii?Q?kO9/EPx3YGhf8sEUHpEZgtaikISo6mwZ0NVYZDurB+ELbV6oSC1enDtdm730?= =?us-ascii?Q?VB4e4OInyzCGsusT5a8kS+3JTGCkeVDjqcWqDDPQjdvsng0VF3NGa/j9bZrr?= =?us-ascii?Q?QMMr5DPcR5nf90TPs1aYpHxJTWYb5DpXXb1AqqACAWX81Km5D6Qyi3ZxaAJT?= =?us-ascii?Q?EhpGQJ1aqR4BKhFVJS/7kkRtCUoJ8JqyIGdkAzdhgeesRSo6HawdZCtatE9a?= =?us-ascii?Q?V9irm8LpptDpQ7qLJ7n1GVYLhJlbARmur9M4FKgXr+8F5hNLzLDoIG2tE96J?= =?us-ascii?Q?XWF3v7wS9wKr4ZLHnmpgs5b6TYMp/JbfXeHHXZAb5I1GCwU4nDpWtOVSaiu2?= =?us-ascii?Q?Le9Xkf6e0OaxxlRcKmSo/D3EDGJG0ik7dYKMlfHTkLLpJUkU8FinpXcNKR/4?= =?us-ascii?Q?m7vuKTzLGat0NXUYjwglHV9vMsQFlY9qT2H/o+lADXc4J/iN1W74Ii3i1xcw?= =?us-ascii?Q?NpG5pQqdoj/8b+J1/HtSYq+PlDfseZSlYXcLvKYgPwOLAaw/hJWG/ZCAfwxx?= =?us-ascii?Q?NXybK1tP4xE8Vdk5i4xVgQHwwGr011UDAq0YveLwfORd4+/NoEP4OMK7AmaF?= =?us-ascii?Q?hKhdqFaWd00YazT6d63vDISnH/ZCoJiPSCNHJ4diX4NqBL7YVMugiCsjbuIl?= =?us-ascii?Q?q1Sl+xTTwLoesjaL3zxrFdhVnAIwUaS2mhGV+xzyKM93j0rs4TMJZ3cxjNlV?= =?us-ascii?Q?7t5pJWTi/3mMq8/beNU=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(1800799024)(82310400026)(36860700013)(7053199007); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2025 16:52:38.0774 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f8e8d79b-cebf-4e4d-7daf-08de26c2e17e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD3.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7223 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org [ upstream commit 3bf9f0f9f0beb8dcd4f3b316c3216a87bc9ab49f ] There is the private API rte_pmd_mlx5_external_sq_enable(), that allows application to create the Send Queue (SQ) on its own and then enable this queue usage as "external SQ". On this enabling call some implicit flows are created to provide compliant SQs behavior - copy metadata register, forward queue originated packet to correct VF, etc. These implicit flows are marked as "external" ones, and there is no cleanup on device start and stop for this kind of flows. Also, PMD has no knowledge if external SQ is still in use by application and implicit cleanup can not be performed. As a result, on multiple device start/stop cycles application re-creates and re-enables many external SQs, causing implicit flow tables overflow. To resolve this issue the rte_pmd_mlx5_external_sq_disable() API is provided, that allows to application to notify PMD the external SQ is not in usage anymore and related implicit flows can be dismissed. Fixes: 26e1eaf2dac4 ("net/mlx5: support device control for E-Switch default rule") Cc: stable@dpdk.org Signed-off-by: Viacheslav Ovsiienko Acked-by: Dariusz Sosnowski --- drivers/net/mlx5/mlx5_flow.h | 12 ++-- drivers/net/mlx5/mlx5_flow_hw.c | 106 +++++++++++++++++++++++++++++++- drivers/net/mlx5/mlx5_trigger.c | 2 +- drivers/net/mlx5/mlx5_txq.c | 54 ++++++++++++++-- drivers/net/mlx5/rte_pmd_mlx5.h | 18 ++++++ drivers/net/mlx5/version.map | 1 + 6 files changed, 181 insertions(+), 12 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index e5672b41f9..234afeb193 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -2632,12 +2632,16 @@ int mlx5_flow_hw_flush_ctrl_flows(struct rte_eth_dev *dev); int mlx5_flow_hw_esw_create_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn, bool external); int mlx5_flow_hw_esw_destroy_sq_miss_flow(struct rte_eth_dev *dev, - uint32_t sqn); + uint32_t sqn, bool external); int mlx5_flow_hw_esw_create_default_jump_flow(struct rte_eth_dev *dev); int mlx5_flow_hw_create_tx_default_mreg_copy_flow(struct rte_eth_dev *dev, - uint32_t sqn, - bool external); -int mlx5_flow_hw_tx_repr_matching_flow(struct rte_eth_dev *dev, uint32_t sqn, bool external); + uint32_t sqn, bool external); +int mlx5_flow_hw_destroy_tx_default_mreg_copy_flow(struct rte_eth_dev *dev, + uint32_t sqn, bool external); +int mlx5_flow_hw_create_tx_repr_matching_flow(struct rte_eth_dev *dev, + uint32_t sqn, bool external); +int mlx5_flow_hw_destroy_tx_repr_matching_flow(struct rte_eth_dev *dev, + uint32_t sqn, bool external); int mlx5_flow_hw_lacp_rx_flow(struct rte_eth_dev *dev); int mlx5_flow_actions_validate(struct rte_eth_dev *dev, const struct rte_flow_actions_template_attr *attr, diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index e3f6e1aa3a..a85b49d284 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -9184,7 +9184,7 @@ flow_hw_is_matching_sq_miss_flow(struct mlx5_hw_ctrl_flow *cf, } int -mlx5_flow_hw_esw_destroy_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn) +mlx5_flow_hw_esw_destroy_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn, bool external) { uint16_t port_id = dev->data->port_id; uint16_t proxy_port_id = dev->data->port_id; @@ -9211,7 +9211,8 @@ mlx5_flow_hw_esw_destroy_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn) !proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_root_tbl || !proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_tbl) return 0; - cf = LIST_FIRST(&proxy_priv->hw_ctrl_flows); + cf = external ? LIST_FIRST(&proxy_priv->hw_ext_ctrl_flows) : + LIST_FIRST(&proxy_priv->hw_ctrl_flows); while (cf != NULL) { cf_next = LIST_NEXT(cf, next); if (flow_hw_is_matching_sq_miss_flow(cf, dev, sqn)) { @@ -9345,8 +9346,58 @@ mlx5_flow_hw_create_tx_default_mreg_copy_flow(struct rte_eth_dev *dev, uint32_t items, 0, copy_reg_action, 0, &flow_info, external); } +static bool +flow_hw_is_matching_tx_mreg_copy_flow(struct mlx5_hw_ctrl_flow *cf, + struct rte_eth_dev *dev, + uint32_t sqn) +{ + if (cf->owner_dev != dev) + return false; + if (cf->info.type == MLX5_HW_CTRL_FLOW_TYPE_TX_META_COPY && cf->info.tx_repr_sq == sqn) + return true; + return false; +} + +int +mlx5_flow_hw_destroy_tx_default_mreg_copy_flow(struct rte_eth_dev *dev, uint32_t sqn, bool external) +{ + uint16_t port_id = dev->data->port_id; + uint16_t proxy_port_id = dev->data->port_id; + struct rte_eth_dev *proxy_dev; + struct mlx5_priv *proxy_priv; + struct mlx5_hw_ctrl_flow *cf; + struct mlx5_hw_ctrl_flow *cf_next; + int ret; + + ret = rte_flow_pick_transfer_proxy(port_id, &proxy_port_id, NULL); + if (ret) { + DRV_LOG(ERR, "Unable to pick transfer proxy port for port %u. Transfer proxy " + "port must be present for default SQ miss flow rules to exist.", + port_id); + return ret; + } + proxy_dev = &rte_eth_devices[proxy_port_id]; + proxy_priv = proxy_dev->data->dev_private; + if (!proxy_priv->dr_ctx || + !proxy_priv->hw_ctrl_fdb || + !proxy_priv->hw_ctrl_fdb->hw_tx_meta_cpy_tbl) + return 0; + cf = external ? LIST_FIRST(&proxy_priv->hw_ext_ctrl_flows) : + LIST_FIRST(&proxy_priv->hw_ctrl_flows); + while (cf != NULL) { + cf_next = LIST_NEXT(cf, next); + if (flow_hw_is_matching_tx_mreg_copy_flow(cf, dev, sqn)) { + claim_zero(flow_hw_destroy_ctrl_flow(proxy_dev, cf->flow)); + LIST_REMOVE(cf, next); + mlx5_free(cf); + } + cf = cf_next; + } + return 0; +} + int -mlx5_flow_hw_tx_repr_matching_flow(struct rte_eth_dev *dev, uint32_t sqn, bool external) +mlx5_flow_hw_create_tx_repr_matching_flow(struct rte_eth_dev *dev, uint32_t sqn, bool external) { struct mlx5_priv *priv = dev->data->dev_private; struct mlx5_rte_flow_item_sq sq_spec = { @@ -9403,6 +9454,55 @@ mlx5_flow_hw_tx_repr_matching_flow(struct rte_eth_dev *dev, uint32_t sqn, bool e items, 0, actions, 0, &flow_info, external); } +static bool +flow_hw_is_tx_matching_repr_matching_flow(struct mlx5_hw_ctrl_flow *cf, + struct rte_eth_dev *dev, + uint32_t sqn) +{ + if (cf->owner_dev != dev) + return false; + if (cf->info.type == MLX5_HW_CTRL_FLOW_TYPE_TX_REPR_MATCH && cf->info.tx_repr_sq == sqn) + return true; + return false; +} + +int +mlx5_flow_hw_destroy_tx_repr_matching_flow(struct rte_eth_dev *dev, uint32_t sqn, bool external) +{ + uint16_t port_id = dev->data->port_id; + uint16_t proxy_port_id = dev->data->port_id; + struct rte_eth_dev *proxy_dev; + struct mlx5_priv *proxy_priv; + struct mlx5_hw_ctrl_flow *cf; + struct mlx5_hw_ctrl_flow *cf_next; + int ret; + + ret = rte_flow_pick_transfer_proxy(port_id, &proxy_port_id, NULL); + if (ret) { + DRV_LOG(ERR, "Unable to pick transfer proxy port for port %u. Transfer proxy " + "port must be present for default SQ miss flow rules to exist.", + port_id); + return ret; + } + proxy_dev = &rte_eth_devices[proxy_port_id]; + proxy_priv = proxy_dev->data->dev_private; + if (!proxy_priv->dr_ctx || + !proxy_priv->hw_tx_repr_tagging_tbl) + return 0; + cf = external ? LIST_FIRST(&proxy_priv->hw_ext_ctrl_flows) : + LIST_FIRST(&proxy_priv->hw_ctrl_flows); + while (cf != NULL) { + cf_next = LIST_NEXT(cf, next); + if (flow_hw_is_tx_matching_repr_matching_flow(cf, dev, sqn)) { + claim_zero(flow_hw_destroy_ctrl_flow(proxy_dev, cf->flow)); + LIST_REMOVE(cf, next); + mlx5_free(cf); + } + cf = cf_next; + } + return 0; +} + int mlx5_flow_hw_lacp_rx_flow(struct rte_eth_dev *dev) { diff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c index 1b19f79822..f72ed7f820 100644 --- a/drivers/net/mlx5/mlx5_trigger.c +++ b/drivers/net/mlx5/mlx5_trigger.c @@ -1495,7 +1495,7 @@ mlx5_traffic_enable_hws(struct rte_eth_dev *dev) } } if (config->dv_esw_en && config->repr_matching) { - if (mlx5_flow_hw_tx_repr_matching_flow(dev, queue, false)) { + if (mlx5_flow_hw_create_tx_repr_matching_flow(dev, queue, false)) { mlx5_txq_release(dev, i); goto error; } diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c index 34c7ef400d..b5dab86e7b 100644 --- a/drivers/net/mlx5/mlx5_txq.c +++ b/drivers/net/mlx5/mlx5_txq.c @@ -1308,7 +1308,7 @@ rte_pmd_mlx5_external_sq_enable(uint16_t port_id, uint32_t sq_num) priv = dev->data->dev_private; if ((!priv->representor && !priv->master) || !priv->sh->config.dv_esw_en) { - DRV_LOG(ERR, "Port %u must be represetnor or master port in E-Switch mode.", + DRV_LOG(ERR, "Port %u must be representor or master port in E-Switch mode.", port_id); rte_errno = EINVAL; return -rte_errno; @@ -1329,9 +1329,9 @@ rte_pmd_mlx5_external_sq_enable(uint16_t port_id, uint32_t sq_num) } if (priv->sh->config.repr_matching && - mlx5_flow_hw_tx_repr_matching_flow(dev, sq_num, true)) { + mlx5_flow_hw_create_tx_repr_matching_flow(dev, sq_num, true)) { if (sq_miss_created) - mlx5_flow_hw_esw_destroy_sq_miss_flow(dev, sq_num); + mlx5_flow_hw_esw_destroy_sq_miss_flow(dev, sq_num, true); return -rte_errno; } @@ -1339,7 +1339,7 @@ rte_pmd_mlx5_external_sq_enable(uint16_t port_id, uint32_t sq_num) priv->sh->config.dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS && mlx5_flow_hw_create_tx_default_mreg_copy_flow(dev, sq_num, true)) { if (sq_miss_created) - mlx5_flow_hw_esw_destroy_sq_miss_flow(dev, sq_num); + mlx5_flow_hw_esw_destroy_sq_miss_flow(dev, sq_num, true); return -rte_errno; } return 0; @@ -1353,6 +1353,52 @@ rte_pmd_mlx5_external_sq_enable(uint16_t port_id, uint32_t sq_num) return -rte_errno; } +int +rte_pmd_mlx5_external_sq_disable(uint16_t port_id, uint32_t sq_num) +{ + struct rte_eth_dev *dev; + struct mlx5_priv *priv; + + if (rte_eth_dev_is_valid_port(port_id) < 0) { + DRV_LOG(ERR, "There is no Ethernet device for port %u.", + port_id); + rte_errno = ENODEV; + return -rte_errno; + } + dev = &rte_eth_devices[port_id]; + priv = dev->data->dev_private; + if ((!priv->representor && !priv->master) || + !priv->sh->config.dv_esw_en) { + DRV_LOG(ERR, "Port %u must be representor or master port in E-Switch mode.", + port_id); + rte_errno = EINVAL; + return -rte_errno; + } + if (sq_num == 0) { + DRV_LOG(ERR, "Invalid SQ number."); + rte_errno = EINVAL; + return -rte_errno; + } +#ifdef HAVE_MLX5_HWS_SUPPORT + if (priv->sh->config.dv_flow_en == 2) { + if (priv->sh->config.fdb_def_rule && + mlx5_flow_hw_esw_destroy_sq_miss_flow(dev, sq_num, true)) + return -rte_errno; + if (priv->sh->config.repr_matching && + mlx5_flow_hw_destroy_tx_repr_matching_flow(dev, sq_num, true)) + return -rte_errno; + if (!priv->sh->config.repr_matching && + priv->sh->config.dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS && + mlx5_flow_hw_destroy_tx_default_mreg_copy_flow(dev, sq_num, true)) + return -rte_errno; + return 0; + } +#endif + /* Not supported for software steering. */ + rte_errno = ENOTSUP; + return -rte_errno; +} + /** * Set the Tx queue dynamic timestamp (mask and offset) * diff --git a/drivers/net/mlx5/rte_pmd_mlx5.h b/drivers/net/mlx5/rte_pmd_mlx5.h index 76c8ad73ca..6166a4d012 100644 --- a/drivers/net/mlx5/rte_pmd_mlx5.h +++ b/drivers/net/mlx5/rte_pmd_mlx5.h @@ -161,6 +161,24 @@ int rte_pmd_mlx5_host_shaper_config(int port_id, uint8_t rate, uint32_t flags); __rte_experimental int rte_pmd_mlx5_external_sq_enable(uint16_t port_id, uint32_t sq_num); +/** + * Disable traffic for external SQ. Should be invoked by application + * before destroying the external SQ. + * + * @param[in] port_id + * The port identifier of the Ethernet device. + * @param[in] sq_num + * SQ HW number. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + * Possible values for rte_errno: + * - EINVAL - invalid sq_number or port type. + * - ENODEV - there is no Ethernet device for this port id. + */ +__rte_experimental +int rte_pmd_mlx5_external_sq_disable(uint16_t port_id, uint32_t sq_num); + #ifdef __cplusplus } #endif diff --git a/drivers/net/mlx5/version.map b/drivers/net/mlx5/version.map index 848270da13..6db031aff4 100644 --- a/drivers/net/mlx5/version.map +++ b/drivers/net/mlx5/version.map @@ -15,4 +15,5 @@ EXPERIMENTAL { # added in 22.07 rte_pmd_mlx5_host_shaper_config; rte_pmd_mlx5_external_sq_enable; + rte_pmd_mlx5_external_sq_disable; }; -- 2.34.1