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Thu, 20 Nov 2025 02:51:10 -0800 From: Shani Peretz To: CC: Shani Peretz , Dariusz Sosnowski , Viacheslav Ovsiienko , "Bing Zhao" , Ori Kam , Suanming Mou , Matan Azrad , Michael Baum Subject: [PATCH 24.11] net/mlx5: fix Tx metadata pattern template mismatch Date: Thu, 20 Nov 2025 12:51:06 +0200 Message-ID: <20251120105106.50721-1-shperetz@nvidia.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023CD:EE_|SJ1PR12MB6076:EE_ X-MS-Office365-Filtering-Correlation-Id: 2b10e79c-c329-475d-1572-08de2822c266 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?uVR9td2373s8EkVRhtTMqE/Nz6lO7BKNkjblvY3pXAtzXDnEVAuHgkTmAoaT?= =?us-ascii?Q?wGGfb65Me21rK+0wx5Qv77dhvyyl9eOKH8iEvTU8bAbMz/oGA0OxOfL5lAFA?= =?us-ascii?Q?OYnSxylOmJGBGo0E0PRtbuaETjBrHmxdgdLPBgIVLcxV5UWRYhXb14fe46bA?= =?us-ascii?Q?ip/Gr8FieQ9Ll938fB7i1UJuBrZmKpvstQQPEqRKhKrFdooJUPxqrffZSqLM?= =?us-ascii?Q?hD1mApPxIWRZNp9q2J1hATQawm51q2PyMUFKkASYVX8zdrC7yCdtp8IVfwPP?= =?us-ascii?Q?XGLI0nS+/FolHA+zwC2n2UCFxCIEkcqq2m5BrxYzPwg8VgRHD4+5UOPJNQjT?= =?us-ascii?Q?BGHxCrVSneX0FcUn81RodgOWSGpNjXEIKrEvuBDNfMKaUSrFRDbuZazZObHy?= =?us-ascii?Q?guJzLl2/sP9BiVR18uAMZX7pByUfY03xj6RZSt+cbih2Hho1AhoETB4FLOM7?= =?us-ascii?Q?5kTugXpo8/Esb3YVS9m0UMNNqyU9YBpTTIMyGVrBCF8LEUb1p8V978cAaWZ8?= =?us-ascii?Q?U7Csqm1wEnTFQUgWYtDOPqfRiu6W54Il+QMH5za+p+ADm7/AWFqoNAUqwXbk?= =?us-ascii?Q?PnNT6qUcOuquDLSxoFz/TanTfZuLdhr/j2O0jGyxwoGHWwNodsqvpiFa+wjn?= =?us-ascii?Q?uMqdkN40kO8rNNHWW6HosRFwJ9sy7aPx8X8PQqs+YCC8bs8C8qB2ZoZJl8P/?= =?us-ascii?Q?ctENFTFERlnjz3iZv7zldvgwXGx2tpdxfgctfAaGpWJUdR1Zu6mAkuCRRmqi?= =?us-ascii?Q?AWz/sGwN3L9M8fRrnU4bh863XLcGeH5uVxlxkSOUp/DqqVMfWLRBlthCyFeP?= =?us-ascii?Q?G886KvLTICGs2DyDTp0QPdXt3kChbXhr6iQgtBclgekigHfhcY9BA5fdixVc?= =?us-ascii?Q?cQVuNbpLplxdhS94sQ7u/fc0F5/Q0IsfxOKwj+KW9xCD89J6KLbRMkN3CUiv?= =?us-ascii?Q?5P1QfT2QJCMEK+aekrw3LphNXKS/PV/Xmq6SYROymnVi817AYxryKDik0tjT?= =?us-ascii?Q?JPxV3SO2mz7jHRz5JCXqN5qhwhRkrbFP3fK262SwVdTCms035aGRjdDeQL+3?= =?us-ascii?Q?2B6M3DR+l4IBe48QLiyspnVVdULMdQwUYjoWrZC5rPaOHmG23fdkD498sZRV?= =?us-ascii?Q?CHrSnK7k4GHsXg9ahmxRxsE6eX1e36fuv6cfrkrnj6qRtLDYuj80K6+/TXyy?= =?us-ascii?Q?CMbo3jlyGFC5dz6yGShXn4L9ECYDpKgmiWx1ajEWGBMAzYVWDQM3xb71Uhpe?= =?us-ascii?Q?khlNlDKluta0E077VdgNPGWCj1bwotxoHq6+QSIeDQcxV9ARpcuqMnr/oIYU?= =?us-ascii?Q?pMdECaSQVcH59FeUW/IGZqmb7NCtdUIYXattVrALGZ1PEsU6R8riH7yfR5F6?= =?us-ascii?Q?gA20d66vTq2l6VuAM2xvaGpxU1XPXhTYa6q/uQWmwPF8om7d9AupFlRw9K0P?= =?us-ascii?Q?6mLQPF5BJwywUzqYOzBSXDkVfTeZlbFU5o6DYqxcihF2EHCn/OZGrtYbbpMy?= =?us-ascii?Q?9w4Bm4M/N7dzsE6iGtHV9OHE8kNuNs1g47wIbVr9urGThWGTbR5uc7ScrMjr?= =?us-ascii?Q?KQs+CW8HJKmQrBFySRg=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Nov 2025 10:51:28.6628 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2b10e79c-c329-475d-1572-08de2822c266 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023CD.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6076 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org When representor matching is disabled with dv_xmeta_en=4, the Tx metadata copy flows use SQ (send queue) pattern matching, but the pattern template was still configured to use ETH match-all pattern. This mismatch causes hardware to reject the flows with error CQEs during port configuration. This patch fixes the issue by using SQ-based pattern template (flow_hw_create_tx_repr_sq_pattern_tmpl) instead of the ETH match-all template (flow_hw_create_tx_default_mreg_copy_pattern_template). Fixes: 593fb3fdfa10 ("net/mlx5: fix multi process Tx default rules") Signed-off-by: Shani Peretz Acked-by: Dariusz Sosnowski --- drivers/net/mlx5/mlx5_flow_hw.c | 42 +-------------------------------- 1 file changed, 1 insertion(+), 41 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 208f50fbfd..b64ba9b46b 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -10185,46 +10185,6 @@ flow_hw_create_ctrl_port_pattern_template(struct rte_eth_dev *dev, return flow_hw_pattern_template_create(dev, &attr, items, error); } -/* - * Creating a flow pattern template with all ETH packets matching. - * This template is used to set up a table for default Tx copy (Tx metadata - * to REG_C_1) flow rule usage. - * - * @param dev - * Pointer to Ethernet device. - * @param error - * Pointer to error structure. - * - * @return - * Pointer to flow pattern template on success, NULL otherwise. - */ -static struct rte_flow_pattern_template * -flow_hw_create_tx_default_mreg_copy_pattern_template(struct rte_eth_dev *dev, - struct rte_flow_error *error) -{ - struct rte_flow_pattern_template_attr tx_pa_attr = { - .relaxed_matching = 0, - .egress = 1, - }; - struct rte_flow_item_eth promisc = { - .hdr.dst_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, - .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, - .hdr.ether_type = 0, - }; - struct rte_flow_item eth_all[] = { - [0] = { - .type = RTE_FLOW_ITEM_TYPE_ETH, - .spec = &promisc, - .mask = &promisc, - }, - [1] = { - .type = RTE_FLOW_ITEM_TYPE_END, - }, - }; - - return flow_hw_pattern_template_create(dev, &tx_pa_attr, eth_all, error); -} - /* * Creating a flow pattern template with all LACP packets matching, only for NIC * ingress domain. @@ -10930,7 +10890,7 @@ flow_hw_create_fdb_ctrl_tables(struct rte_eth_dev *dev, struct rte_flow_error *e /* Create templates and table for default Tx metadata copy flow rule. */ if (!repr_matching && xmeta == MLX5_XMETA_MODE_META32_HWS) { hw_ctrl_fdb->tx_meta_items_tmpl = - flow_hw_create_tx_default_mreg_copy_pattern_template(dev, error); + flow_hw_create_tx_repr_sq_pattern_tmpl(dev, error); if (!hw_ctrl_fdb->tx_meta_items_tmpl) { DRV_LOG(ERR, "port %u failed to Tx metadata copy pattern" " template for control flows", dev->data->port_id); -- 2.34.1