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Thu, 20 Nov 2025 10:45:32 -0800 From: Shani Peretz To: CC: Shani Peretz , Dariusz Sosnowski , Matan Azrad , Viacheslav Ovsiienko , Michael Baum Subject: [PATCH 22.11 v2] net/mlx5: fix Tx metadata pattern template mismatch Date: Thu, 20 Nov 2025 20:45:21 +0200 Message-ID: <20251120184521.1713304-1-shperetz@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251120104823.50618-1-shperetz@nvidia.com> References: <20251120104823.50618-1-shperetz@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF000000A0:EE_|CH3PR12MB8993:EE_ X-MS-Office365-Filtering-Correlation-Id: f72a6aa4-237f-4490-16f0-08de2865082c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|376014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?nD1d1Pu5cRGhrZnJShVsQaTo6d8pDRRH75TKaG4ZdWAWNIX+uUwe2/+t+qVf?= =?us-ascii?Q?hJOaMg2e6fzpNjYn1Gtn368bslWu2Jk6VG+gllZWebR3v2QQbDmjTUEdWZFj?= =?us-ascii?Q?dRnfjbOOxN6sxKV+qqUVkybXhOducIFNnWC75Lf4wja2VBDYsAbgtgDBUIB4?= =?us-ascii?Q?bOirjErmTsiJmvA8cw7Wok/o4TciOrXlaZ9BuksYsF2QJrM597q7qoqyQRjq?= =?us-ascii?Q?bHOjKwgSLCanIfXnQ4SwrLjOqghvaWMWER5BcyL54Dkbdi+U/gdfmN+3x/pq?= =?us-ascii?Q?/O6F5FNDircrig9KN5w+r5T9VvAgTjjHIsWkPqu9BsXe6abobihbVFTg2Oyt?= =?us-ascii?Q?mshYOb6S5BBC0PbcnW50SgOddKOyV3wS+9IVN5gNeUkwLCpBJKkBf6ZLvHfi?= =?us-ascii?Q?Gn4J6NDByzC7gp9ISaU9HKx4DzCu1XsP0Ip1MFb8JTRZf2SvHFFtIW2rRf7q?= =?us-ascii?Q?FjgvtBUUTcphWLsAxbCLBs7pZzYF5lZpxau5DL6cj3FL6CA8IFk2Hu9bnPcv?= =?us-ascii?Q?thc/B0kXXkMxtgux/dJuTrGGkhkkrzlbRPFJ4CY/eTxSqde0sgU8Iz5Pw5ma?= =?us-ascii?Q?wpHJpdbH2wAcn0VkaFu1/01f1JChirW5i+nAWeNQ/lkEZHYHACoZrZB9nxh9?= =?us-ascii?Q?mMN9K+Lr7ZV5MxX732Qy8LoHnhgdaNLzjY5rnVGjXktgFCcAUsj1tT/ZzrNC?= =?us-ascii?Q?ZnEGmg4K3Gh55S/d5AyykczLNlw4MZH245CuRZ1lGgx619hSHHPL/p4+EfnP?= =?us-ascii?Q?wZ8OIX9vsIptakDyl2e4aAlpi6NvBWtlr/IiT5Z/frdXKMkMZEGoGblT6j6y?= =?us-ascii?Q?Fy0i3s7UCytX05l5DlQmAhr9/b0naniDCdDUlLyxDKz2XM6xJHbHDey1IHcC?= =?us-ascii?Q?0KMp+xN6W1pcURE36UE1Qq5oTYZZgaB2dDHMrRECZrRni4iuNSEAZFKPhZKS?= =?us-ascii?Q?20vw7zxwiXrpN1gK3nF40vA69C2nWVEI/cgBHH0hJt6xsviXldERx4C4P1+A?= =?us-ascii?Q?aD9p12N0q2G8mMb6vlE0FaB6G9ADKsmvWQ7mUH47F4RkrESzqtLc5XIFmD/L?= =?us-ascii?Q?grvOpzoRe+H2O0ywaVXciNOUjmpZDL6tIb3Ag/h+YNL+7tTzZL+FZaLLwcyd?= =?us-ascii?Q?AEXaAhT8lIE/3zewIgdwPdtVTRP89GF6UY0iDblzy82LsSdwlhZfzgSKGZ8G?= =?us-ascii?Q?DhG7GIz8K4DH33jkL5dyR+hTA22wSsK0bbIVMpUA4N1pPsUeOThyEMiTy32+?= =?us-ascii?Q?13k69FHs54jNdr8RFI+K8XteXm7e/aefHjdmSz+74mPfV2kD4jR9v7pySNtx?= =?us-ascii?Q?8VPw4xlRkOcfvIC1t/e1I20tshGT1g9W6cY9PQ7OSuGd+TYtvnvPP1ZLmEcX?= =?us-ascii?Q?+uTKhuhPAOsLRipKupSUAcxpx8IHLos7dROcyIjskqWd2vu3eaFeujxaApHI?= =?us-ascii?Q?vWU4lgj0OzQe8mvLzFO0BPiuJ5etSgot4HWaYV1rqqPfjJBChr+COgmbd7g8?= =?us-ascii?Q?gxCvMxxaPJgnPW24ky7ictclFlwWGFniYR5CkR+RSuiLleC8HnWk0QZvz589?= =?us-ascii?Q?1rJEiTfeucr0wM6BKxU=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(376014)(36860700013)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Nov 2025 18:45:52.5472 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f72a6aa4-237f-4490-16f0-08de2865082c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF000000A0.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8993 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org When representor matching is disabled with dv_xmeta_en=4, the Tx metadata copy flows use SQ (send queue) pattern matching, but the pattern template was still configured to use ETH match-all pattern. This mismatch causes hardware to reject the flows with error CQEs during port configuration. This patch fixes the issue by using SQ-based pattern template (flow_hw_create_tx_repr_sq_pattern_tmpl) instead of the ETH match-all template (flow_hw_create_tx_default_mreg_copy_pattern_template). Fixes: 4f0537afcc45 ("net/mlx5: fix multi-process Tx default rules") Signed-off-by: Shani Peretz Acked-by: Dariusz Sosnowski --- drivers/net/mlx5/mlx5_flow_hw.c | 42 +-------------------------------- 1 file changed, 1 insertion(+), 41 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index a85b49d284..1ca8c8cd80 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -5781,46 +5781,6 @@ flow_hw_create_ctrl_port_pattern_template(struct rte_eth_dev *dev, return flow_hw_pattern_template_create(dev, &attr, items, error); } -/* - * Creating a flow pattern template with all ETH packets matching. - * This template is used to set up a table for default Tx copy (Tx metadata - * to REG_C_1) flow rule usage. - * - * @param dev - * Pointer to Ethernet device. - * @param error - * Pointer to error structure. - * - * @return - * Pointer to flow pattern template on success, NULL otherwise. - */ -static struct rte_flow_pattern_template * -flow_hw_create_tx_default_mreg_copy_pattern_template(struct rte_eth_dev *dev, - struct rte_flow_error *error) -{ - struct rte_flow_pattern_template_attr tx_pa_attr = { - .relaxed_matching = 0, - .egress = 1, - }; - struct rte_flow_item_eth promisc = { - .dst.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, - .src.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, - .type = 0, - }; - struct rte_flow_item eth_all[] = { - [0] = { - .type = RTE_FLOW_ITEM_TYPE_ETH, - .spec = &promisc, - .mask = &promisc, - }, - [1] = { - .type = RTE_FLOW_ITEM_TYPE_END, - }, - }; - - return flow_hw_pattern_template_create(dev, &tx_pa_attr, eth_all, error); -} - /* * Creating a flow pattern template with all LACP packets matching, only for NIC * ingress domain. @@ -6523,7 +6483,7 @@ flow_hw_create_ctrl_tables(struct rte_eth_dev *dev, struct rte_flow_error *error /* Create templates and table for default Tx metadata copy flow rule. */ if (!repr_matching && xmeta == MLX5_XMETA_MODE_META32_HWS) { hw_ctrl_fdb->tx_meta_items_tmpl = - flow_hw_create_tx_default_mreg_copy_pattern_template(dev, error); + flow_hw_create_tx_repr_sq_pattern_tmpl(dev, error); if (!hw_ctrl_fdb->tx_meta_items_tmpl) { DRV_LOG(ERR, "port %u failed to Tx metadata copy pattern" " template for control flows", dev->data->port_id); -- 2.34.1