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Thu, 25 Dec 2025 01:21:53 -0800 From: Shani Peretz To: Jiawen Wu CC: dpdk stable Subject: patch 'net/txgbe: reduce memory size of ring descriptors' has been queued to stable release 23.11.6 Date: Thu, 25 Dec 2025 11:17:54 +0200 Message-ID: <20251225091938.345892-33-shperetz@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251225091938.345892-1-shperetz@nvidia.com> References: <20251221145746.763179-93-shperetz@nvidia.com> <20251225091938.345892-1-shperetz@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636D:EE_|DM3PR12MB9435:EE_ X-MS-Office365-Filtering-Correlation-Id: be7a7644-c107-40cc-1316-08de439712f0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|1800799024|36860700013|82310400026|13003099007|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?kWElMrMKcMbHYB6YLQ1suM4miQdX/eY+acqsM07HaleiTlJmFD+YnGP1vfL1?= =?us-ascii?Q?+3mVPid/OaOzkX/VOX3iVWlt8em2zZvzTDt0snBVOYQ4T9+iXH9ucOOmG4sI?= =?us-ascii?Q?vCdatRAC+n4sahf73QzOsG107MGPzAX0qHl5lmRNB2gJTPbMvLeKR02dSAEa?= =?us-ascii?Q?KnNBr5jq3w/N8zPQD0kIFjXVCS7zQvKuCCJAkxRSKucs0AL0K+eT7qwSJohk?= =?us-ascii?Q?wTyb8mn7zyToyHZ17hKqGaw6wB4kEqR9nxJDENy19OHIXH2P09RLpJ4Z4391?= =?us-ascii?Q?FVR8HGsjGZGUULydJezyg6y/abYIny5JZLkgz4sUVVrdxCl3YnfBR6CFd/xH?= =?us-ascii?Q?WBfRaalz/Af0vSs2UhJ1ciPmNmN5lBezaypFl/ack33XS94efppaDMHD7Gqo?= =?us-ascii?Q?/AolLy2UHk4QSd8DrI6oTcV+KtYXbjdF9Q1+CuQ0Bh++zHGhBRHnYFCGME3G?= =?us-ascii?Q?GR02GpFetCtF8mw4ee8Am/4McS9tkUf0AVkT4mzhujdWEeg16sZhW1VjypfI?= =?us-ascii?Q?yRfY6celrbVA/juTtSbe8bSCwpH5UhlUEdcXPmWArvmf1Pf0jAa8bEczT9A1?= =?us-ascii?Q?31Nx0rB84iA4DKexrfRgmUwugWcpw3R3WqhIQM4W/Wps1xBrejivv8AXYVTg?= =?us-ascii?Q?S5iykIWF14SFL6YcwfbIN8Ruozupt3OQSgYHQXN9W5GczUnYnzR8YeGJdeKV?= =?us-ascii?Q?+80sQwMUoCUFo8FG8rqyufoYuiNqeJshY7ldS/pirGUwJEt80k7VhWNAjQdT?= =?us-ascii?Q?Ur0xuzdLrdIV00J/AHLA4bXxgO7HXj1v2Lm3845LBXaBT7mgdK6GJK6OeHhL?= =?us-ascii?Q?JmHxDZHEg9IJVG7LOhyjcGJ5IWkMaMANS8AiIqzD1gy7ftGa3Iwscx7dizGR?= =?us-ascii?Q?Gl28gQYNRpm3xOF1YJSUUtAfWIsciL351VZTK5BBjDVD5DykIJrQqOzorKqD?= =?us-ascii?Q?Ff0AVyasqM7yr6q5xuGy0IJ9CJpcPY+kAWH6h1qmcwfV3dojapR5RGL4b4Su?= =?us-ascii?Q?JGv5GrfkIvlMMZVnvZUMF6eB9BZyDXLuRGIMio++ZVMxTzH9OAVyF6bE45fw?= =?us-ascii?Q?dxI2210Uh35dwaQFIg5HrBGg6wDnY38PS42oSEH0atFjI52dyNncGyFjD/qO?= =?us-ascii?Q?5V9uGB61afSZLVqNRg//u+3PG10XFOkdAWd/P6fCb3yD93awO5UjOfFPKrnT?= =?us-ascii?Q?nvGPuc2zCADWAPgc7RcwX8L/Gr8mlfQZt3dZjgs4upgmSn47Jz/lt2NfVIzF?= =?us-ascii?Q?P3PV2X/wo2KIP6D5zb264OC0tNK5sEXh0qU0DHcbD/AMOhFxHIa8wigTk6Wj?= =?us-ascii?Q?vDvVSvRg9V2XBQtXjhtoFg63cZdQWsxFxqM2s38HZ4Jpq661ETUcsUOMxvcF?= =?us-ascii?Q?2P0eUeShHmT/XgHrvyr3WBhI6GpaHVbF5LW199GYKLswWZeBccckPHIultBH?= =?us-ascii?Q?A72c91XbJB/AEy5Hc7ApnB+c8CjA/MnfJNQWdnvaI/Hav7o5rOQSWf2SBiOt?= =?us-ascii?Q?7qV4j/BO9MuIIiBMsDLuF7G5QHpB406yR0XjyqEcKIRq7yMlzg2nFti6uY1K?= =?us-ascii?Q?4rbfFaKtzVstM7scH8RLPBtMupURsjcSpcMn2TrX?= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026)(13003099007)(7053199007); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Dec 2025 09:22:06.8629 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: be7a7644-c107-40cc-1316-08de439712f0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM3PR12MB9435 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 23.11.6 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 12/30/25. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/shanipr/dpdk-stable This queued commit can be viewed at: https://github.com/shanipr/dpdk-stable/commit/ef169a015e35f90a9a1ccf9e014d23f8b010dbc3 Thanks. Shani --- >From ef169a015e35f90a9a1ccf9e014d23f8b010dbc3 Mon Sep 17 00:00:00 2001 From: Jiawen Wu Date: Mon, 27 Oct 2025 11:15:26 +0800 Subject: [PATCH] net/txgbe: reduce memory size of ring descriptors [ upstream commit 843c59d1c2cef10a75037ebc73460f2ed28f9839 ] The memory of ring descriptors was allocated in size of the maximum ring size. It seems not friendly to our hardware on some domestic platforms. Change it to allocate in size of the real ring size. Fixes: 226bf98eda87 ("net/txgbe: add Rx and Tx queues setup and release") Signed-off-by: Jiawen Wu --- drivers/net/txgbe/txgbe_rxtx.c | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/drivers/net/txgbe/txgbe_rxtx.c b/drivers/net/txgbe/txgbe_rxtx.c index 12d8deb072..89865ec606 100644 --- a/drivers/net/txgbe/txgbe_rxtx.c +++ b/drivers/net/txgbe/txgbe_rxtx.c @@ -2335,13 +2335,9 @@ txgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, if (txq == NULL) return -ENOMEM; - /* - * Allocate TX ring hardware descriptors. A memzone large enough to - * handle the maximum ring size is allocated in order to allow for - * resizing in later calls to the queue setup function. - */ + /* Allocate TX ring hardware descriptors. */ tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx, - sizeof(struct txgbe_tx_desc) * TXGBE_RING_DESC_MAX, + sizeof(struct txgbe_tx_desc) * nb_desc, TXGBE_ALIGN, socket_id); if (tz == NULL) { txgbe_tx_queue_release(txq); @@ -2579,6 +2575,7 @@ txgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t len; struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev); uint64_t offloads; + uint32_t size; PMD_INIT_FUNC_TRACE(); hw = TXGBE_DEV_HW(dev); @@ -2629,13 +2626,10 @@ txgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, */ rxq->pkt_type_mask = TXGBE_PTID_MASK; - /* - * Allocate RX ring hardware descriptors. A memzone large enough to - * handle the maximum ring size is allocated in order to allow for - * resizing in later calls to the queue setup function. - */ + /* Allocate RX ring hardware descriptors. */ + size = (nb_desc + RTE_PMD_TXGBE_RX_MAX_BURST) * sizeof(struct txgbe_rx_desc); rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx, - RX_RING_SZ, TXGBE_ALIGN, socket_id); + size, TXGBE_ALIGN, socket_id); if (rz == NULL) { txgbe_rx_queue_release(rxq); return -ENOMEM; @@ -2645,7 +2639,7 @@ txgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, /* * Zero init all the descriptors in the ring. */ - memset(rz->addr, 0, RX_RING_SZ); + memset(rz->addr, 0, size); /* * Modified to setup VFRDT for Virtual Function -- 2.43.0 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2025-12-25 11:16:37.956554518 +0200 +++ 0033-net-txgbe-reduce-memory-size-of-ring-descriptors.patch 2025-12-25 11:16:35.544846000 +0200 @@ -1 +1 @@ -From 843c59d1c2cef10a75037ebc73460f2ed28f9839 Mon Sep 17 00:00:00 2001 +From ef169a015e35f90a9a1ccf9e014d23f8b010dbc3 Mon Sep 17 00:00:00 2001 @@ -5,0 +6,2 @@ +[ upstream commit 843c59d1c2cef10a75037ebc73460f2ed28f9839 ] + @@ -11 +12,0 @@ -Cc: stable@dpdk.org @@ -19 +20 @@ -index c606180741..d77db1efa2 100644 +index 12d8deb072..89865ec606 100644 @@ -22 +23 @@ -@@ -2521,13 +2521,9 @@ txgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, +@@ -2335,13 +2335,9 @@ txgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, @@ -38 +39 @@ -@@ -2781,6 +2777,7 @@ txgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, +@@ -2579,6 +2575,7 @@ txgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, @@ -46 +47 @@ -@@ -2831,13 +2828,10 @@ txgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, +@@ -2629,13 +2626,10 @@ txgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, @@ -63 +64 @@ -@@ -2847,7 +2841,7 @@ txgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, +@@ -2645,7 +2639,7 @@ txgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,