From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E150F470E5 for ; Thu, 25 Dec 2025 10:23:39 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E29EA4065E; Thu, 25 Dec 2025 10:23:28 +0100 (CET) Received: from CO1PR03CU002.outbound.protection.outlook.com (mail-westus2azon11010016.outbound.protection.outlook.com [52.101.46.16]) by mails.dpdk.org (Postfix) with ESMTP id 289284065D for ; Thu, 25 Dec 2025 10:23:27 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=qYzNbJ3VsOnl3gk2aAXsfm7iy+Zao4hQYHdpg4c83zyGN7jdekljUuiY4OnezJkBH98SpfcPKZQsr3NI5rcyDNHCmYYcN73J0YWp1MumkBPz/EOUsA8v0gm8LzpaRwKUqhOImbWutqRwNm8jLji2kBtQ6Cq5afoOmL0YW3t5REmQQpSNQjZWCwu9W1REYFncfJMiMdGsG1LwkY54QIz4kM0HjxCzp2/Ghh+DpZ3bJA9fUu842NXYAZvi+eIYvxPBQMjAc6RI+Lo+d4UA0naLH34JcsAWYGsdm82AsHoznJhabEFuNi4FgnA57SGIth0OzLGzSAR31VgJcz9fBnL7Ag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=EApwMrlaZI/jVvIbu5CIpJi47bdaSyf/xYpmy3jdJxE=; b=VMyBr8sNNehJxs4yOWJpZ0feV3xKFsU4F2QSLjOM7OebLLysoE96iBood++3zZMFbohe8kLoU0cpPOTy44nZu+Sef8lFhhTqXFpvZX6xH2kDjCQxKvdgm6mYfoJMgGxfaztmx2RcwNqIdsIadjDY4aCKXQiSvKig56fEA7wAOMq0N2WVHS582uchDnx76Y3Bv/W8fdhUYmtnBwkNlgbmTObrmiP5djMRUKnKaPh0i0fY+pa+4QYbnthe4RF4W20a4+wgCZQGURK7jZ7gBuJGDcv3hNCrOzLpUm7gTac1RKH6vCfI4KMVFirqZrIPKe80ZNOAhZ1n0Y7Ii+i3xAGoOA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=EApwMrlaZI/jVvIbu5CIpJi47bdaSyf/xYpmy3jdJxE=; b=Nof96nDJwt6IvnqV7WW3aennLTo3+oU0VHM36+ITBjMLgKJfy9EfwfJHNguC/xnfC0FeSWT5ZsOori+6GR80fG5U/02wvWxI1i05ywQ3GgGKWeAAy/a93bRL/Ktp83CSbqjjESUEtqVY48J11hsP09Esm6AK6mY1wqeFQf/tqOPC6BGsDBhdbbb3X8oc2YcZaWgf0mu0yDIzh0R8oCINhC7ynOPc2u0ZwLbiyh9XWoULrRVSfpeyC6/ZG7juorgKX9GpX7HYpB0ji28QAF2bOviZQqR93Lhl5jyibZvaf6h7WkMAtHztj2cibZcVQNgV/HxtIt4Ihd/kpC86xW7wPQ== Received: from CH0PR04CA0036.namprd04.prod.outlook.com (2603:10b6:610:77::11) by DS7PR12MB6024.namprd12.prod.outlook.com (2603:10b6:8:84::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9456.11; Thu, 25 Dec 2025 09:23:19 +0000 Received: from CH2PEPF0000013E.namprd02.prod.outlook.com (2603:10b6:610:77:cafe::66) by CH0PR04CA0036.outlook.office365.com (2603:10b6:610:77::11) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9456.12 via Frontend Transport; Thu, 25 Dec 2025 09:23:08 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by CH2PEPF0000013E.mail.protection.outlook.com (10.167.244.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9456.9 via Frontend Transport; Thu, 25 Dec 2025 09:23:19 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 25 Dec 2025 01:23:12 -0800 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 25 Dec 2025 01:23:12 -0800 Received: from nvidia.com (10.127.8.12) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Thu, 25 Dec 2025 01:23:10 -0800 From: Shani Peretz To: Michael Baum CC: Dariusz Sosnowski , dpdk stable Subject: patch 'net/mlx5: fix multi-process Tx default rules' has been queued to stable release 23.11.6 Date: Thu, 25 Dec 2025 11:18:12 +0200 Message-ID: <20251225091938.345892-51-shperetz@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251225091938.345892-1-shperetz@nvidia.com> References: <20251221145746.763179-93-shperetz@nvidia.com> <20251225091938.345892-1-shperetz@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000013E:EE_|DS7PR12MB6024:EE_ X-MS-Office365-Filtering-Correlation-Id: 36424933-1014-4031-8a98-08de43973e5e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|1800799024|82310400026|36860700013|13003099007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?YkxMFbhbbZ6Lr7Mmak+KI6LJGbapPbo6R/Z6q5hdVBKfVVXCNmMfYbe1L1wP?= =?us-ascii?Q?pPMVXJeD1V0htbqXFsLd/biKMmRwMO99XYwmJrVhxBxvCSumULfjaURBu5BN?= =?us-ascii?Q?3/YMAvx4RIZ3yWEbX2+cMWStCCj/5l90L4eojorL7cJw+ve4ehlzWUNDu2Mz?= =?us-ascii?Q?kWnSVm2To7/QvDLr0mTGSyvUlYWZCXsU8EIbk55Yj3UlPxhAQyiZFq46TrUp?= =?us-ascii?Q?uk8Du4E2rVz75EpAW5LmRxgc2tYJ047EfI4CrWXnmXImGrDsq3AxGsfxulwa?= =?us-ascii?Q?iIPPht+iHRzip9+rtZXN9218ovvKktY97MlY9lRH7KeohWhhzDaj9CHC9lPR?= =?us-ascii?Q?XAZtejXfhsXepeBGPgjv8hMnbCcpAa1YVoGxWkJQ6V01dRl9MbjzoYo2phX7?= =?us-ascii?Q?RADfsCMaFYNl1ErwMxzXejIpIFGwqQj+3IQX32JfrgH/5VBk55YDtXDVchwo?= =?us-ascii?Q?vIjrgsiZjA9aHTptHcbOs7o7MQFUeAFdk1NP9HazQ2YBuu08XiZpYzfoL+BA?= =?us-ascii?Q?P8wOL2dAUS1244NWL6R3NF1GAqXTCkdzVCExxsDmKzcsoEbNSg0zsNuB4Mnu?= =?us-ascii?Q?Lh0R+ksV6dJIibaqSsZv71AHSFvkSvzGA6QAqsD97IY/uXPekKP7imsfAQe8?= =?us-ascii?Q?7bkPwOZx8S3UNCPM/22YA6XnvSb/+f/KJ0seQdEVPNNSR88JKHKdBm+t128h?= =?us-ascii?Q?5F5Ax0C8ZwMO96GUiAAUwwamy6s0uSmBU0pIEN0NjINN8IXkHfeqy4AobUYj?= =?us-ascii?Q?TdRuWHfcJZ29j1w/ZSmFEhumeLCu8q5+1PYbVl+c44xHXz+NGOaY4wH/w3/x?= =?us-ascii?Q?9V+l6BHyTkk0lEwGT4nk2rHlJVODnVcqLPaKkwmW0ri9TMt3VcDdkYWJg+ab?= =?us-ascii?Q?Lm7uLAdM0Qfsr/kkmh4pDVSW+fyuYUP7W7BsD3gkfDyJuPobK5oKkbGmGCS9?= =?us-ascii?Q?XEo/AAruowqabVjFuIBYOSU/8pE9IJz3CiPhsGOeNz0XcrvB50zYy8QcrY8L?= =?us-ascii?Q?O8FAdP/H/a5FTn5BHlTldIGl2T7ICQnusA6TtMOT7Ug+MdcOA/ZyCM/BQyMT?= =?us-ascii?Q?+zQ5gZfzDeUHukWWgkaiO+syhsGn2PYk79SNfg2M6/usZUtSJmY8m5OefOKE?= =?us-ascii?Q?3iVO1JBOiZjJ80Kmzee60a983S9IzxQHqI4TIkIfdk4JWsub1EnBnm6UzUzm?= =?us-ascii?Q?tjeEgCyhsrHn8f0Y2I6REL8CkPSOz3H3U27RnT2d381FqL1DjpBqiDCfK1TF?= =?us-ascii?Q?gxjz5mkOqdqx2Wr+mqGlkm5atIckucK/nHaPT5u0lJeUx4pdndhhr270THwn?= =?us-ascii?Q?soVEr7hUw1BYzjgpflcuSiAw1v8zjWAiu6zR/3E2Fpk4S3sf0YoARhgF3Sj+?= =?us-ascii?Q?pxG2ZW1cp1pwkzVWbZo9EZ/aUJBSdbuvXU7Kg6U/qH1Lk4PiFEBBKxyxilOR?= =?us-ascii?Q?5EndIHeY8NCpyfwI6FW0N8/OkDSUE3MM0620pxHi8n9EQIOsR+6Rym+Ex98+?= =?us-ascii?Q?Ng9jfTdM2+E+0yQ7mjl8hopRb398GY+t3BK9y8kT9b9YZc977UHGnlk8wY+F?= =?us-ascii?Q?XSN3FCDLKZXsRYZeEkUDgAsjfcsF3UvuvNCsKTiD?= X-Forefront-Antispam-Report: CIP:216.228.118.232; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(1800799024)(82310400026)(36860700013)(13003099007); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Dec 2025 09:23:19.7492 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 36424933-1014-4031-8a98-08de43973e5e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000013E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6024 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 23.11.6 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 12/30/25. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/shanipr/dpdk-stable This queued commit can be viewed at: https://github.com/shanipr/dpdk-stable/commit/9e7df70a2c6cad155f3e7e8917658dc5c1e28b8a Thanks. Shani --- >From 9e7df70a2c6cad155f3e7e8917658dc5c1e28b8a Mon Sep 17 00:00:00 2001 From: Michael Baum Date: Wed, 29 Oct 2025 17:57:08 +0200 Subject: [PATCH] net/mlx5: fix multi-process Tx default rules [ upstream commit 2f1bb792ad51aeb2da00198a63422fc478131bd5 ] When representor matching is disabled, an egress default rule is inserted which matches all and copies REG_A to REG_C_1 (when dv_xmeta_en == 4) and jump to group 1. All user rules started from group 1. When 2 processes are working together, the first one creates this flow rule and the second one is failed with errno EEXIST. This renders all user egress rules in 2nd process to be invalid. This patch changes this default rule match on SQs. Fixes: 483181f7b6dd ("net/mlx5: support device control of representor matching") Signed-off-by: Michael Baum Acked-by: Dariusz Sosnowski --- drivers/net/mlx5/mlx5_flow.h | 4 +++- drivers/net/mlx5/mlx5_flow_hw.c | 24 +++++++++++------------- drivers/net/mlx5/mlx5_trigger.c | 25 +++++++++++++------------ drivers/net/mlx5/mlx5_txq.c | 8 ++++++++ 4 files changed, 35 insertions(+), 26 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 805b346d3c..219ea462c9 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -2919,7 +2919,9 @@ int mlx5_flow_hw_esw_create_sq_miss_flow(struct rte_eth_dev *dev, int mlx5_flow_hw_esw_destroy_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn); int mlx5_flow_hw_esw_create_default_jump_flow(struct rte_eth_dev *dev); -int mlx5_flow_hw_create_tx_default_mreg_copy_flow(struct rte_eth_dev *dev); +int mlx5_flow_hw_create_tx_default_mreg_copy_flow(struct rte_eth_dev *dev, + uint32_t sqn, + bool external); int mlx5_flow_hw_tx_repr_matching_flow(struct rte_eth_dev *dev, uint32_t sqn, bool external); int mlx5_flow_hw_lacp_rx_flow(struct rte_eth_dev *dev); int mlx5_flow_actions_validate(struct rte_eth_dev *dev, diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index eff4d36f8f..41910d801b 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -8413,7 +8413,7 @@ flow_hw_create_tx_default_mreg_copy_table(struct rte_eth_dev *dev, .priority = MLX5_HW_LOWEST_PRIO_ROOT, .egress = 1, }, - .nb_flows = 1, /* One default flow rule for all. */ + .nb_flows = MLX5_HW_CTRL_FLOW_NB_RULES, }; struct mlx5_flow_template_table_cfg tx_tbl_cfg = { .attr = tx_tbl_attr, @@ -12304,21 +12304,18 @@ mlx5_flow_hw_esw_create_default_jump_flow(struct rte_eth_dev *dev) } int -mlx5_flow_hw_create_tx_default_mreg_copy_flow(struct rte_eth_dev *dev) +mlx5_flow_hw_create_tx_default_mreg_copy_flow(struct rte_eth_dev *dev, uint32_t sqn, bool external) { struct mlx5_priv *priv = dev->data->dev_private; - struct rte_flow_item_eth promisc = { - .hdr.dst_addr.addr_bytes = "\x00\x00\x00\x00\x00\x00", - .hdr.src_addr.addr_bytes = "\x00\x00\x00\x00\x00\x00", - .hdr.ether_type = 0, + struct mlx5_rte_flow_item_sq sq_spec = { + .queue = sqn, }; - struct rte_flow_item eth_all[] = { - [0] = { - .type = RTE_FLOW_ITEM_TYPE_ETH, - .spec = &promisc, - .mask = &promisc, + struct rte_flow_item items[] = { + { + .type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ, + .spec = &sq_spec, }, - [1] = { + { .type = RTE_FLOW_ITEM_TYPE_END, }, }; @@ -12348,6 +12345,7 @@ mlx5_flow_hw_create_tx_default_mreg_copy_flow(struct rte_eth_dev *dev) }; struct mlx5_hw_ctrl_flow_info flow_info = { .type = MLX5_HW_CTRL_FLOW_TYPE_TX_META_COPY, + .tx_repr_sq = sqn, }; MLX5_ASSERT(priv->master); @@ -12357,7 +12355,7 @@ mlx5_flow_hw_create_tx_default_mreg_copy_flow(struct rte_eth_dev *dev) return 0; return flow_hw_create_ctrl_flow(dev, dev, priv->hw_ctrl_fdb->hw_tx_meta_cpy_tbl, - eth_all, 0, copy_reg_action, 0, &flow_info, false); + items, 0, copy_reg_action, 0, &flow_info, external); } int diff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c index f870aaf797..51d848158c 100644 --- a/drivers/net/mlx5/mlx5_trigger.c +++ b/drivers/net/mlx5/mlx5_trigger.c @@ -1479,18 +1479,6 @@ mlx5_traffic_enable_hws(struct rte_eth_dev *dev) unsigned int i; int ret; - /* - * With extended metadata enabled, the Tx metadata copy is handled by default - * Tx tagging flow rules, so default Tx flow rule is not needed. It is only - * required when representor matching is disabled. - */ - if (config->dv_esw_en && - !config->repr_matching && - config->dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS && - priv->master) { - if (mlx5_flow_hw_create_tx_default_mreg_copy_flow(dev)) - goto error; - } for (i = 0; i < priv->txqs_n; ++i) { struct mlx5_txq_ctrl *txq = mlx5_txq_get(dev, i); uint32_t queue; @@ -1512,6 +1500,19 @@ mlx5_traffic_enable_hws(struct rte_eth_dev *dev) goto error; } } + /* + * With extended metadata enabled, the Tx metadata copy is handled by default + * Tx tagging flow rules, so default Tx flow rule is not needed. It is only + * required when representor matching is disabled. + */ + if (config->dv_esw_en && !config->repr_matching && + config->dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS && + (priv->master || priv->representor)) { + if (mlx5_flow_hw_create_tx_default_mreg_copy_flow(dev, queue, false)) { + mlx5_txq_release(dev, i); + goto error; + } + } mlx5_txq_release(dev, i); } if (config->fdb_def_rule) { diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c index 1ddd360a64..3f8d861180 100644 --- a/drivers/net/mlx5/mlx5_txq.c +++ b/drivers/net/mlx5/mlx5_txq.c @@ -1334,6 +1334,14 @@ rte_pmd_mlx5_external_sq_enable(uint16_t port_id, uint32_t sq_num) mlx5_flow_hw_esw_destroy_sq_miss_flow(dev, sq_num); return -rte_errno; } + + if (!priv->sh->config.repr_matching && + priv->sh->config.dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS && + mlx5_flow_hw_create_tx_default_mreg_copy_flow(dev, sq_num, true)) { + if (sq_miss_created) + mlx5_flow_hw_esw_destroy_sq_miss_flow(dev, sq_num); + return -rte_errno; + } return 0; } #endif -- 2.43.0 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2025-12-25 11:16:38.849588524 +0200 +++ 0051-net-mlx5-fix-multi-process-Tx-default-rules.patch 2025-12-25 11:16:35.789984000 +0200 @@ -1 +1 @@ -From 2f1bb792ad51aeb2da00198a63422fc478131bd5 Mon Sep 17 00:00:00 2001 +From 9e7df70a2c6cad155f3e7e8917658dc5c1e28b8a Mon Sep 17 00:00:00 2001 @@ -5,0 +6,2 @@ +[ upstream commit 2f1bb792ad51aeb2da00198a63422fc478131bd5 ] + @@ -17 +18,0 @@ -Cc: stable@dpdk.org @@ -29 +30 @@ -index c525516672..c5905ebfac 100644 +index 805b346d3c..219ea462c9 100644 @@ -32 +33 @@ -@@ -3565,7 +3565,9 @@ int mlx5_flow_hw_esw_create_sq_miss_flow(struct rte_eth_dev *dev, +@@ -2919,7 +2919,9 @@ int mlx5_flow_hw_esw_create_sq_miss_flow(struct rte_eth_dev *dev, @@ -44 +45 @@ -index 491a78a0de..d945c88eb0 100644 +index eff4d36f8f..41910d801b 100644 @@ -47 +48 @@ -@@ -10643,7 +10643,7 @@ flow_hw_create_tx_default_mreg_copy_table(struct rte_eth_dev *dev, +@@ -8413,7 +8413,7 @@ flow_hw_create_tx_default_mreg_copy_table(struct rte_eth_dev *dev, @@ -56 +57 @@ -@@ -16004,21 +16004,18 @@ mlx5_flow_hw_esw_create_default_jump_flow(struct rte_eth_dev *dev) +@@ -12304,21 +12304,18 @@ mlx5_flow_hw_esw_create_default_jump_flow(struct rte_eth_dev *dev) @@ -65,2 +66,2 @@ -- .hdr.dst_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, -- .hdr.src_addr.addr_bytes = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, +- .hdr.dst_addr.addr_bytes = "\x00\x00\x00\x00\x00\x00", +- .hdr.src_addr.addr_bytes = "\x00\x00\x00\x00\x00\x00", @@ -86 +87 @@ -@@ -16048,6 +16045,7 @@ mlx5_flow_hw_create_tx_default_mreg_copy_flow(struct rte_eth_dev *dev) +@@ -12348,6 +12345,7 @@ mlx5_flow_hw_create_tx_default_mreg_copy_flow(struct rte_eth_dev *dev) @@ -88,2 +89,2 @@ - struct mlx5_ctrl_flow_info flow_info = { - .type = MLX5_CTRL_FLOW_TYPE_TX_META_COPY, + struct mlx5_hw_ctrl_flow_info flow_info = { + .type = MLX5_HW_CTRL_FLOW_TYPE_TX_META_COPY, @@ -94 +95 @@ -@@ -16057,7 +16055,7 @@ mlx5_flow_hw_create_tx_default_mreg_copy_flow(struct rte_eth_dev *dev) +@@ -12357,7 +12355,7 @@ mlx5_flow_hw_create_tx_default_mreg_copy_flow(struct rte_eth_dev *dev) @@ -104 +105 @@ -index 916ac03c16..e6acb56d4d 100644 +index f870aaf797..51d848158c 100644 @@ -107 +108 @@ -@@ -1606,18 +1606,6 @@ mlx5_traffic_enable_hws(struct rte_eth_dev *dev) +@@ -1479,18 +1479,6 @@ mlx5_traffic_enable_hws(struct rte_eth_dev *dev) @@ -126 +127 @@ -@@ -1639,6 +1627,19 @@ mlx5_traffic_enable_hws(struct rte_eth_dev *dev) +@@ -1512,6 +1500,19 @@ mlx5_traffic_enable_hws(struct rte_eth_dev *dev) @@ -147 +148 @@ -index b090d8274d..834ca541d5 100644 +index 1ddd360a64..3f8d861180 100644 @@ -150 +151 @@ -@@ -1459,6 +1459,14 @@ rte_pmd_mlx5_external_sq_enable(uint16_t port_id, uint32_t sq_num) +@@ -1334,6 +1334,14 @@ rte_pmd_mlx5_external_sq_enable(uint16_t port_id, uint32_t sq_num)