patch 'ring: establish safe partial order in default mode' has been queued to stable release 23.11.6

[Shani Peretz <shperetz@nvidia.com>]

Hi,

FYI, your patch has been queued to stable release 23.11.6

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 12/30/25. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://github.com/shanipr/dpdk-stable

This queued commit can be viewed at:
https://github.com/shanipr/dpdk-stable/commit/942163a489126848c2ae10fcb60df2fb59f3aac8

Thanks.

Shani

---
From 942163a489126848c2ae10fcb60df2fb59f3aac8 Mon Sep 17 00:00:00 2001
From: Wathsala Vithanage <wathsala.vithanage@arm.com>
Date: Tue, 2 Dec 2025 20:39:26 +0000
Subject: [PATCH] ring: establish safe partial order in default mode
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

[ upstream commit a4ad0eba9def1d1d071da8afe5e96eb2a2e0d71f]

The function __rte_ring_headtail_move_head() assumes that the barrier
(fence) between the load of the head and the load-acquire of the
opposing tail guarantees the following: if a first thread reads tail
and then writes head and a second thread reads the new value of head
and then reads tail, then it should observe the same (or a later)
value of tail.

This assumption is incorrect under the C11 memory model. If the barrier
(fence) is intended to establish a total ordering of ring operations,
it fails to do so. Instead, the current implementation only enforces a
partial ordering, which can lead to unsafe interleavings. In particular,
some partial orders can cause underflows in free slot or available
element computations, potentially resulting in data corruption.

The issue manifests when a CPU first acts as a producer and later as a
consumer. In this scenario, the barrier assumption may fail when another
core takes the consumer role. A Herd7 litmus test in C11 can demonstrate
this violation. The problem has not been widely observed so far because:
  (a) on strong memory models (e.g., x86-64) the assumption holds, and
  (b) on relaxed models with RCsc semantics the ordering is still strong
      enough to prevent hazards.
The problem becomes visible only on weaker models, when load-acquire is
implemented with RCpc semantics (e.g. some AArch64 CPUs which support
the LDAPR and LDAPUR instructions).

Three possible solutions exist:
  1. Strengthen ordering by upgrading release/acquire semantics to
     sequential consistency. This requires using seq-cst for stores,
     loads, and CAS operations. However, this approach introduces a
     significant performance penalty on relaxed-memory architectures.

  2. Establish a safe partial order by enforcing a pair-wise
     happens-before relationship between thread of same role by changing
     the CAS and the preceding load of the head by converting them to
     release and acquire respectively. This approach makes the original
     barrier assumption unnecessary and allows its removal.

  3. Retain partial ordering but ensure only safe partial orders are
     committed. This can be done by detecting underflow conditions
     (producer < consumer) and quashing the update in such cases.
     This approach makes the original barrier assumption unnecessary
     and allows its removal.

This patch implements solution (2) to preserve the “enqueue always
succeeds” contract expected by dependent libraries (e.g., mempool).
While solution (3) offers higher performance, adopting it now would
break that assumption.

Signed-off-by: Wathsala Vithanage <wathsala.vithanage@arm.com>
Signed-off-by: Ola Liljedahl <ola.liljedahl@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Reviewed-by: Dhruv Tripathi <dhruv.tripathi@arm.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@huawei.com>
Tested-by: Konstantin Ananyev <konstantin.ananyev@huawei.com>
---
 lib/ring/rte_ring_c11_pvt.h | 71 ++++++++++++++++++++++++++++---------
 1 file changed, 54 insertions(+), 17 deletions(-)

diff --git a/lib/ring/rte_ring_c11_pvt.h b/lib/ring/rte_ring_c11_pvt.h
index 5c10ad88f5..fb00889fdf 100644
--- a/lib/ring/rte_ring_c11_pvt.h
+++ b/lib/ring/rte_ring_c11_pvt.h
@@ -24,7 +24,12 @@ __rte_ring_update_tail(struct rte_ring_headtail *ht, uint32_t old_val,
 	if (!single)
 		rte_wait_until_equal_32((uint32_t *)(uintptr_t)&ht->tail, old_val,
 			rte_memory_order_relaxed);
-
+	/*
+	 * R0: Establishes a synchronizing edge with load-acquire of
+	 * cons_tail at A1 or prod_tail at A4.
+	 * Ensures that memory effects by this thread on ring elements array
+	 * is observed by a different thread of the other type.
+	 */
 	rte_atomic_store_explicit(&ht->tail, new_val, rte_memory_order_release);
 }
 
@@ -62,16 +67,24 @@ __rte_ring_move_prod_head(struct rte_ring *r, unsigned int is_sp,
 	unsigned int max = n;
 	int success;
 
-	*old_head = rte_atomic_load_explicit(&r->prod.head, rte_memory_order_relaxed);
+	/*
+	 * A0: Establishes a synchronizing edge with R1.
+	 * Ensure that this thread observes same values
+	 * to cons_tail observed by the thread that
+	 * updated r->prod.head.
+	 * If not, an unsafe partial order may ensue.
+	 */
+	*old_head = rte_atomic_load_explicit(&r->prod.head, rte_memory_order_acquire);
 	do {
 		/* Reset n to the initial burst count */
 		n = max;
 
-		/* Ensure the head is read before tail */
-		__atomic_thread_fence(rte_memory_order_acquire);
 
-		/* load-acquire synchronize with store-release of ht->tail
-		 * in update_tail.
+		/*
+		 * A1: Establishes a synchronizing edge with R0.
+		 * Ensures that other thread's memory effects on
+		 * ring elements array is observed by the time
+		 * this thread observes its tail update.
 		 */
 		cons_tail = rte_atomic_load_explicit(&r->cons.tail,
 					rte_memory_order_acquire);
@@ -97,10 +110,19 @@ __rte_ring_move_prod_head(struct rte_ring *r, unsigned int is_sp,
 			success = 1;
 		} else
 			/* on failure, *old_head is updated */
+			/*
+			 * R1/A2.
+			 * R1: Establishes a synchronizing edge with A0 of a
+			 * different thread.
+			 * A2: Establishes a synchronizing edge with R1 of a
+			 * different thread to observe same value for
+			 * cons_tail observed by that thread on CAS failure
+			 * (to retry with an updated *old_head).
+			 */
 			success = rte_atomic_compare_exchange_strong_explicit(&r->prod.head,
 					old_head, *new_head,
-					rte_memory_order_relaxed,
-					rte_memory_order_relaxed);
+					rte_memory_order_release,
+					rte_memory_order_acquire);
 	} while (unlikely(success == 0));
 	return n;
 }
@@ -138,17 +160,23 @@ __rte_ring_move_cons_head(struct rte_ring *r, int is_sc,
 	uint32_t prod_tail;
 	int success;
 
-	/* move cons.head atomically */
-	*old_head = rte_atomic_load_explicit(&r->cons.head, rte_memory_order_relaxed);
+	/*
+	 * A3: Establishes a synchronizing edge with R2.
+	 * Ensure that this thread observes same values
+	 * to prod_tail observed by the thread that
+	 * updated r->cons.head.
+	 * If not, an unsafe partial order may ensue.
+	 */
+	*old_head = rte_atomic_load_explicit(&r->cons.head, rte_memory_order_acquire);
 	do {
 		/* Restore n as it may change every loop */
 		n = max;
 
-		/* Ensure the head is read before tail */
-		__atomic_thread_fence(rte_memory_order_acquire);
-
-		/* this load-acquire synchronize with store-release of ht->tail
-		 * in update_tail.
+		/*
+		 * A4: Establishes a synchronizing edge with R0.
+		 * Ensures that other thread's memory effects on
+		 * ring elements array is observed by the time
+		 * this thread observes its tail update.
 		 */
 		prod_tail = rte_atomic_load_explicit(&r->prod.tail,
 					rte_memory_order_acquire);
@@ -173,10 +201,19 @@ __rte_ring_move_cons_head(struct rte_ring *r, int is_sc,
 			success = 1;
 		} else
 			/* on failure, *old_head will be updated */
+			/*
+			 * R2/A5.
+			 * R2: Establishes a synchronizing edge with A3 of a
+			 * different thread.
+			 * A5: Establishes a synchronizing edge with R2 of a
+			 * different thread to observe same value for
+			 * prod_tail observed by that thread on CAS failure
+			 * (to retry with an updated *old_head).
+			 */
 			success = rte_atomic_compare_exchange_strong_explicit(&r->cons.head,
 							old_head, *new_head,
-							rte_memory_order_relaxed,
-							rte_memory_order_relaxed);
+							rte_memory_order_release,
+							rte_memory_order_acquire);
 	} while (unlikely(success == 0));
 	return n;
 }
-- 
2.43.0

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2025-12-25 11:16:39.805462717 +0200
+++ 0069-ring-establish-safe-partial-order-in-default-mode.patch	2025-12-25 11:16:36.069837000 +0200
@@ -0,0 +1,194 @@
+From 942163a489126848c2ae10fcb60df2fb59f3aac8 Mon Sep 17 00:00:00 2001
+From: Wathsala Vithanage <wathsala.vithanage@arm.com>
+Date: Tue, 2 Dec 2025 20:39:26 +0000
+Subject: [PATCH] ring: establish safe partial order in default mode
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+[ upstream commit a4ad0eba9def1d1d071da8afe5e96eb2a2e0d71f]
+
+The function __rte_ring_headtail_move_head() assumes that the barrier
+(fence) between the load of the head and the load-acquire of the
+opposing tail guarantees the following: if a first thread reads tail
+and then writes head and a second thread reads the new value of head
+and then reads tail, then it should observe the same (or a later)
+value of tail.
+
+This assumption is incorrect under the C11 memory model. If the barrier
+(fence) is intended to establish a total ordering of ring operations,
+it fails to do so. Instead, the current implementation only enforces a
+partial ordering, which can lead to unsafe interleavings. In particular,
+some partial orders can cause underflows in free slot or available
+element computations, potentially resulting in data corruption.
+
+The issue manifests when a CPU first acts as a producer and later as a
+consumer. In this scenario, the barrier assumption may fail when another
+core takes the consumer role. A Herd7 litmus test in C11 can demonstrate
+this violation. The problem has not been widely observed so far because:
+  (a) on strong memory models (e.g., x86-64) the assumption holds, and
+  (b) on relaxed models with RCsc semantics the ordering is still strong
+      enough to prevent hazards.
+The problem becomes visible only on weaker models, when load-acquire is
+implemented with RCpc semantics (e.g. some AArch64 CPUs which support
+the LDAPR and LDAPUR instructions).
+
+Three possible solutions exist:
+  1. Strengthen ordering by upgrading release/acquire semantics to
+     sequential consistency. This requires using seq-cst for stores,
+     loads, and CAS operations. However, this approach introduces a
+     significant performance penalty on relaxed-memory architectures.
+
+  2. Establish a safe partial order by enforcing a pair-wise
+     happens-before relationship between thread of same role by changing
+     the CAS and the preceding load of the head by converting them to
+     release and acquire respectively. This approach makes the original
+     barrier assumption unnecessary and allows its removal.
+
+  3. Retain partial ordering but ensure only safe partial orders are
+     committed. This can be done by detecting underflow conditions
+     (producer < consumer) and quashing the update in such cases.
+     This approach makes the original barrier assumption unnecessary
+     and allows its removal.
+
+This patch implements solution (2) to preserve the “enqueue always
+succeeds” contract expected by dependent libraries (e.g., mempool).
+While solution (3) offers higher performance, adopting it now would
+break that assumption.
+
+Signed-off-by: Wathsala Vithanage <wathsala.vithanage@arm.com>
+Signed-off-by: Ola Liljedahl <ola.liljedahl@arm.com>
+Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
+Reviewed-by: Dhruv Tripathi <dhruv.tripathi@arm.com>
+Acked-by: Konstantin Ananyev <konstantin.ananyev@huawei.com>
+Tested-by: Konstantin Ananyev <konstantin.ananyev@huawei.com>
+---
+ lib/ring/rte_ring_c11_pvt.h | 71 ++++++++++++++++++++++++++++---------
+ 1 file changed, 54 insertions(+), 17 deletions(-)
+
+diff --git a/lib/ring/rte_ring_c11_pvt.h b/lib/ring/rte_ring_c11_pvt.h
+index 5c10ad88f5..fb00889fdf 100644
+--- a/lib/ring/rte_ring_c11_pvt.h
++++ b/lib/ring/rte_ring_c11_pvt.h
+@@ -24,7 +24,12 @@ __rte_ring_update_tail(struct rte_ring_headtail *ht, uint32_t old_val,
+ 	if (!single)
+ 		rte_wait_until_equal_32((uint32_t *)(uintptr_t)&ht->tail, old_val,
+ 			rte_memory_order_relaxed);
+-
++	/*
++	 * R0: Establishes a synchronizing edge with load-acquire of
++	 * cons_tail at A1 or prod_tail at A4.
++	 * Ensures that memory effects by this thread on ring elements array
++	 * is observed by a different thread of the other type.
++	 */
+ 	rte_atomic_store_explicit(&ht->tail, new_val, rte_memory_order_release);
+ }
+ 
+@@ -62,16 +67,24 @@ __rte_ring_move_prod_head(struct rte_ring *r, unsigned int is_sp,
+ 	unsigned int max = n;
+ 	int success;
+ 
+-	*old_head = rte_atomic_load_explicit(&r->prod.head, rte_memory_order_relaxed);
++	/*
++	 * A0: Establishes a synchronizing edge with R1.
++	 * Ensure that this thread observes same values
++	 * to cons_tail observed by the thread that
++	 * updated r->prod.head.
++	 * If not, an unsafe partial order may ensue.
++	 */
++	*old_head = rte_atomic_load_explicit(&r->prod.head, rte_memory_order_acquire);
+ 	do {
+ 		/* Reset n to the initial burst count */
+ 		n = max;
+ 
+-		/* Ensure the head is read before tail */
+-		__atomic_thread_fence(rte_memory_order_acquire);
+ 
+-		/* load-acquire synchronize with store-release of ht->tail
+-		 * in update_tail.
++		/*
++		 * A1: Establishes a synchronizing edge with R0.
++		 * Ensures that other thread's memory effects on
++		 * ring elements array is observed by the time
++		 * this thread observes its tail update.
+ 		 */
+ 		cons_tail = rte_atomic_load_explicit(&r->cons.tail,
+ 					rte_memory_order_acquire);
+@@ -97,10 +110,19 @@ __rte_ring_move_prod_head(struct rte_ring *r, unsigned int is_sp,
+ 			success = 1;
+ 		} else
+ 			/* on failure, *old_head is updated */
++			/*
++			 * R1/A2.
++			 * R1: Establishes a synchronizing edge with A0 of a
++			 * different thread.
++			 * A2: Establishes a synchronizing edge with R1 of a
++			 * different thread to observe same value for
++			 * cons_tail observed by that thread on CAS failure
++			 * (to retry with an updated *old_head).
++			 */
+ 			success = rte_atomic_compare_exchange_strong_explicit(&r->prod.head,
+ 					old_head, *new_head,
+-					rte_memory_order_relaxed,
+-					rte_memory_order_relaxed);
++					rte_memory_order_release,
++					rte_memory_order_acquire);
+ 	} while (unlikely(success == 0));
+ 	return n;
+ }
+@@ -138,17 +160,23 @@ __rte_ring_move_cons_head(struct rte_ring *r, int is_sc,
+ 	uint32_t prod_tail;
+ 	int success;
+ 
+-	/* move cons.head atomically */
+-	*old_head = rte_atomic_load_explicit(&r->cons.head, rte_memory_order_relaxed);
++	/*
++	 * A3: Establishes a synchronizing edge with R2.
++	 * Ensure that this thread observes same values
++	 * to prod_tail observed by the thread that
++	 * updated r->cons.head.
++	 * If not, an unsafe partial order may ensue.
++	 */
++	*old_head = rte_atomic_load_explicit(&r->cons.head, rte_memory_order_acquire);
+ 	do {
+ 		/* Restore n as it may change every loop */
+ 		n = max;
+ 
+-		/* Ensure the head is read before tail */
+-		__atomic_thread_fence(rte_memory_order_acquire);
+-
+-		/* this load-acquire synchronize with store-release of ht->tail
+-		 * in update_tail.
++		/*
++		 * A4: Establishes a synchronizing edge with R0.
++		 * Ensures that other thread's memory effects on
++		 * ring elements array is observed by the time
++		 * this thread observes its tail update.
+ 		 */
+ 		prod_tail = rte_atomic_load_explicit(&r->prod.tail,
+ 					rte_memory_order_acquire);
+@@ -173,10 +201,19 @@ __rte_ring_move_cons_head(struct rte_ring *r, int is_sc,
+ 			success = 1;
+ 		} else
+ 			/* on failure, *old_head will be updated */
++			/*
++			 * R2/A5.
++			 * R2: Establishes a synchronizing edge with A3 of a
++			 * different thread.
++			 * A5: Establishes a synchronizing edge with R2 of a
++			 * different thread to observe same value for
++			 * prod_tail observed by that thread on CAS failure
++			 * (to retry with an updated *old_head).
++			 */
+ 			success = rte_atomic_compare_exchange_strong_explicit(&r->cons.head,
+ 							old_head, *new_head,
+-							rte_memory_order_relaxed,
+-							rte_memory_order_relaxed);
++							rte_memory_order_release,
++							rte_memory_order_acquire);
+ 	} while (unlikely(success == 0));
+ 	return n;
+ }
+-- 
+2.43.0
+