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Thu, 25 Dec 2025 01:25:39 -0800 From: Shani Peretz To: Sivaprasad Tummala CC: dpdk stable Subject: patch 'net/mlx5: fix spurious CPU wakeups' has been queued to stable release 23.11.6 Date: Thu, 25 Dec 2025 11:18:48 +0200 Message-ID: <20251225091938.345892-87-shperetz@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251225091938.345892-1-shperetz@nvidia.com> References: <20251221145746.763179-93-shperetz@nvidia.com> <20251225091938.345892-1-shperetz@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00026367:EE_|DS4PR12MB9747:EE_ X-MS-Office365-Filtering-Correlation-Id: c41e1aaa-f83e-4ae4-7776-08de439796d9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|36860700013|1800799024|82310400026|7053199007|13003099007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?YKNEy/W1pY83DqCJFUD5NriWkWQ0Fj49qISIZkRmJDLk3djwQJ0Pm0kuYqsl?= =?us-ascii?Q?q+/eXttIzt8jL1mLkdPdjjSih02vZZMu2p9DJWQa7TZ9Uzfo2xvcqcPg+4vg?= =?us-ascii?Q?YkHtjRmMSTzlBi6KLBIy20bRXUkDNi8Fct9kRbMbvcfpN4xCo/gBaDoqSnpP?= =?us-ascii?Q?gAy5UjCSGNn+lZCTcKp5p3oPmZ6cwJwpQomQ3mUPUNHeMSUd/sS0udWM9Ayo?= =?us-ascii?Q?k182zXxztz7dg5QIuIecCA8SOKFOqIh/0IQCXRzMjM++gVE0sJo8MMUetOAc?= =?us-ascii?Q?kbt3cMTswGg1a48+pqo/t7gEUTLRtKu3TKnV4nKAwK73nq8OtvtbgCB43SFB?= =?us-ascii?Q?3ADr5/2g8RNcmt2qwZJHQFFjEbyWl1iWF8koWdtwszPu9rn/ZCPPPua/fsiH?= =?us-ascii?Q?2x/hPNdBNnMS1X5PLPWzdbeal+nu3q7n8nOlcYeoyIr5rQzUZyAa/GXYu/xA?= =?us-ascii?Q?RdLGtML1bynbEO51GOwNvJjsEWygFWhxM0ajEdf4JTKj/gZaCnzkaZ7t0saI?= =?us-ascii?Q?N0sU/Y24ZOx4kW4puYiVxiBT9tVV26jJsh+jTZ5MBfvddI1AKv2VZL4Wcle1?= =?us-ascii?Q?X7CTM1rQ9tUJ+brYtuaksBw/gRgF6nNm3Yb20A6K+n3+NNJQwSIOZvg7/79A?= =?us-ascii?Q?2uSgSabIAdX74Qptpvp+ageYYMHjJ2qe43LJzMneeF2Pd5jzA3IFjRNtnJ0p?= =?us-ascii?Q?Dbmuulu7W2mmuhUrCR0rMHZqNRtEUPyGoRqW6bg3Rl0DNn/ZM9FzD2mTK8Kj?= =?us-ascii?Q?Z6TrVs4OU/pXqpMymW3cwygQJNRdAMeQ1rSxlnkZ5GjpX644kPZUC17PLV+l?= =?us-ascii?Q?tZfENHvDKQu4Ykj9mZktoSH4K+u67N7CJpscwZifqPN8mxqHjaeFuC/gvGaH?= =?us-ascii?Q?NvOCU4Ox3xy3m+Aipglfu1zgyWx2WcTty3xJeA6FowxiSnyw0AqezFJiLlHX?= =?us-ascii?Q?U+uXlfuZLyInd87UcOWw1MXlWmv56bzqV5Guc0IfMcvKyFP4sWxumcmBYNsd?= =?us-ascii?Q?nqkLWyy41xJcEV4kiKrSCTMGFAMjWIXQd93VsHCe9o46K99ynyTMVw17akyT?= =?us-ascii?Q?g5ZbwHavQf+653Y3TfNmKYsLimk6mfC37g+RJ1qZca+M73tdiUBctGzChQZ7?= =?us-ascii?Q?y5isGwF9ShFu+rBeIPBGTZuCSdmJk9NdWuR+ufKkDiysly2Rw7yzxKryXeMl?= =?us-ascii?Q?0JEZc1s29S5wE3aLBFD7TZhX0u8EQ7luB/b+DYlk79cJ8gIkbvYKECCgMg1g?= =?us-ascii?Q?hu3yDbpDxmey6ZgRWBlcdGqrfu5bosSGlYhivTrgyJIm8QNqP6OHld0KoAPj?= =?us-ascii?Q?lxzCrqG0JMQyoTeYWWKSt0y11XBcTzparlmkRCc0LrZl455OmLSJFUs60ItX?= =?us-ascii?Q?TP7CCTfjFRkwm/5rc/Sjzfop81389zmrujZVhSupXBdD/4t1rahrlmOFNf7I?= =?us-ascii?Q?1HSPtJkA7+YoRWZ81JqJ6fd0Lq7zrCDp8G+4IyiRXFkLTRjqrScADF8XMTJR?= =?us-ascii?Q?m7H2j1cUIAWY6CxJmEVUAV9Nj713jeqw3WpkfNmfwo5IMYgspkY819uEUYjO?= =?us-ascii?Q?K8TV1ZUh30Doe+/Y8eg=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(36860700013)(1800799024)(82310400026)(7053199007)(13003099007); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Dec 2025 09:25:48.2305 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c41e1aaa-f83e-4ae4-7776-08de439796d9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00026367.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS4PR12MB9747 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 23.11.6 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 12/30/25. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/shanipr/dpdk-stable This queued commit can be viewed at: https://github.com/shanipr/dpdk-stable/commit/601473b4dffb60a6ff279cdc32000cb681308448 Thanks. Shani --- >From 601473b4dffb60a6ff279cdc32000cb681308448 Mon Sep 17 00:00:00 2001 From: Sivaprasad Tummala Date: Tue, 11 Nov 2025 03:40:57 +0000 Subject: [PATCH] net/mlx5: fix spurious CPU wakeups [ upstream commit 750f635fc6a7ee287e076c5500ca97d77187676a ] Previously, the PMD used a common monitor callback to determine CQE ownership for power-aware polling. However, when a CQE contained an invalid opcode (MLX5_CQE_INVALID), ownership bit was not reliable. As a result, the monitor condition could falsely indicate CQE availability and cause the CPU to wake up unnecessarily during low traffic periods. This resulted in spurious wakeups in monitor-wait mode and reduced the expected power savings, as cores exited the sleep state even when no valid CQEs were available. This patch introduces a dedicated callback that skips invalid CQEs and optimizes power efficiency by preventing false wakeups caused by hardware-owned or invalid entries. Fixes: a8f0df6bf98d ("net/mlx5: support power monitoring") Signed-off-by: Sivaprasad Tummala --- drivers/net/mlx5/mlx5_rx.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/mlx5_rx.c b/drivers/net/mlx5/mlx5_rx.c index 73d9f23a65..d704d34c75 100644 --- a/drivers/net/mlx5/mlx5_rx.c +++ b/drivers/net/mlx5/mlx5_rx.c @@ -294,6 +294,20 @@ mlx5_monitor_callback(const uint64_t value, return (value & m) == v ? -1 : 0; } +static int +mlx5_monitor_cqe_own_callback(const uint64_t value, + const uint64_t opaque[RTE_POWER_MONITOR_OPAQUE_SZ]) +{ + const uint64_t m = opaque[CLB_MSK_IDX]; + const uint64_t v = opaque[CLB_VAL_IDX]; + const uint64_t sw_owned = ((value & m) == v); + const uint64_t opcode = MLX5_CQE_OPCODE(value); + const uint64_t valid_op = (opcode != MLX5_CQE_INVALID); + + /* ownership bit is not valid for invalid opcode; CQE is HW owned */ + return -(valid_op & sw_owned); +} + int mlx5_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc) { struct mlx5_rxq_data *rxq = rx_queue; @@ -311,12 +325,13 @@ int mlx5_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc) pmc->addr = &cqe->validity_iteration_count; pmc->opaque[CLB_VAL_IDX] = vic; pmc->opaque[CLB_MSK_IDX] = MLX5_CQE_VIC_INIT; + pmc->fn = mlx5_monitor_callback; } else { pmc->addr = &cqe->op_own; pmc->opaque[CLB_VAL_IDX] = !!idx; pmc->opaque[CLB_MSK_IDX] = MLX5_CQE_OWNER_MASK; + pmc->fn = mlx5_monitor_cqe_own_callback; } - pmc->fn = mlx5_monitor_callback; pmc->size = sizeof(uint8_t); return 0; } -- 2.43.0 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2025-12-25 11:16:40.646042101 +0200 +++ 0087-net-mlx5-fix-spurious-CPU-wakeups.patch 2025-12-25 11:16:36.215835000 +0200 @@ -1 +1 @@ -From 750f635fc6a7ee287e076c5500ca97d77187676a Mon Sep 17 00:00:00 2001 +From 601473b4dffb60a6ff279cdc32000cb681308448 Mon Sep 17 00:00:00 2001 @@ -5,0 +6,2 @@ +[ upstream commit 750f635fc6a7ee287e076c5500ca97d77187676a ] + @@ -22 +23,0 @@ -Cc: stable@dpdk.org @@ -30 +31 @@ -index 420a03068d..ac663a978e 100644 +index 73d9f23a65..d704d34c75 100644 @@ -33 +34 @@ -@@ -295,6 +295,20 @@ mlx5_monitor_callback(const uint64_t value, +@@ -294,6 +294,20 @@ mlx5_monitor_callback(const uint64_t value, @@ -54 +55 @@ -@@ -312,12 +326,13 @@ int mlx5_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc) +@@ -311,12 +325,13 @@ int mlx5_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)