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Thu, 25 Dec 2025 01:26:03 -0800 From: Shani Peretz To: Dariusz Sosnowski CC: dpdk stable Subject: patch 'net/mlx5: fix flow tag indexes support on root table' has been queued to stable release 23.11.6 Date: Thu, 25 Dec 2025 11:18:55 +0200 Message-ID: <20251225091938.345892-94-shperetz@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251225091938.345892-1-shperetz@nvidia.com> References: <20251221145746.763179-93-shperetz@nvidia.com> <20251225091938.345892-1-shperetz@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000FCC3:EE_|PH7PR12MB6442:EE_ X-MS-Office365-Filtering-Correlation-Id: c51ab5db-3358-44d0-b0f6-08de4397a817 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|82310400026|376014|36860700013|13003099007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?yfSYwQMZumfrqt+uiFltfUyxLklTR3Sfyojoul2f6+zDDaoNr1eNH3eBhHeJ?= =?us-ascii?Q?q5jZPy1UgDdpShROnupIMsFvZMHRda3PnwQfkKjkXFjbo6eMqx1dvFTkCaEh?= =?us-ascii?Q?8Hbcmxy/NLa9PcHHD0KLa/417ZLzj27c/46Gk6FaYRYYfLyFilIcbtRdluC3?= =?us-ascii?Q?izkph0Tikf9cAH9d8iACE6x900+vqCqyEFVI6a+LUVjA/arbdf4stN90X36V?= =?us-ascii?Q?xzI+0oTW7VLlcpW17FacHNfRv+R7jTjyMUkf1ZCwNKWzyWO9DPao1S3nGCUD?= =?us-ascii?Q?xbhMbMl7zU67hSHF/RBTPh77qiAP5ao6xw8XSm67ezM1hl+I4a2XlGUf1Pml?= =?us-ascii?Q?bHMJqWfPv8h+FYrPmCNkDvFKQqOsh6tf9GUFUOsUrFmYaptclUdr1WgHeIro?= =?us-ascii?Q?Xyb+KeD9EH+HCOB4vY+0HvoKJESigE8hiZIMc5waa4aleyVjl2VtYFXjzi2p?= =?us-ascii?Q?8VQjmJ3IoX88q0liY9FjYD08+pb03KyTZgYbePbq3RSo7YeVMc08PsYrlIyh?= =?us-ascii?Q?7Fx1sTB0xbylHyHdX9KgX2Cn6jSxVv/RxUaev5mg1bcCx9KQZsdI5pfMB9EX?= =?us-ascii?Q?L48au9KFYlb7qowrONFVVEKC1B7FXUQ8j4uvs7KAN9q97OOY1nMj0OGabSRB?= =?us-ascii?Q?8SV+B7pRnu1apSenAdhvNHUbl9d82eDyQIj+xfOWJzwXXedw1wNGoYeUYA8T?= =?us-ascii?Q?cFKN15/01uSEr7UBFIRka6YhKsYH4cc/+fkwbXgexa6Pbej0TXllek48S4W5?= =?us-ascii?Q?DtPKeFb302QaoQJqT6G9RMCC/XDMjEo/AV/r3R51FGczkl70Yf5vLO1yGr+p?= =?us-ascii?Q?fApl2pkoDHCjtpArNP25eK/i/Ou4xVwVGnXm39aWhWfQ4r6pYaf8MMVb2YEN?= =?us-ascii?Q?Bnu1GQp6Z5fSyjJf0Ij12LRdBQGsyRzgBwKGwGzGQ4e940cN7SXcm9f6ARtj?= =?us-ascii?Q?S/bVyie1ztuaG4x4MdNCRfhVPgD0AL5yedLfR1cncQs2qAMReEvOyWPsKrs9?= =?us-ascii?Q?ePHWVHO9Dp/9//U/4jeRcVlVF//Q6nleVG063YauWJrnPxhHU5T8BajSFcWy?= =?us-ascii?Q?MfskL70vMEf6nfj7UVcoOCH12c07VT35+SfOpqs5OuXzatILAxpxrFE2aKdl?= =?us-ascii?Q?bcyJtIUe+0ZcuX4G7xBq6sjhXjeushfFLwzFFbxAUHVHESSLe1szq/ic6/L3?= =?us-ascii?Q?5vcN7pOT7oWRTGm6u6ehGAX2lsqHJjK4hFL6MP7/r72XrSh2qGhvuzv3iKHV?= =?us-ascii?Q?roHU5k+u4f2S1aQc4+gipiXJVTlLd1Trk5cwkxkzsSAh38WJSyds/aV+9ny2?= =?us-ascii?Q?0j4QuKxuSKENx+/Ht9fIa1+IYQipgGz+KKXV0CteJvjpU8Ap6sTBOJADAaHL?= =?us-ascii?Q?C8fRABgKIBtSkNus53xH/3PlzE9UFVLVRAKyn4ZfQNObVnMOxw7Lu39wbpoF?= =?us-ascii?Q?ISYzEaa3AQLM1ggLw2UcuMn6pt5n4dYBoN1gcbtSLilFeXtorHFSb7s44jjU?= =?us-ascii?Q?xw8yGqN/ygw4XS3mI/pyzfkowDFwKC13/NeR7+iNnFOxCMfUakDuPkKa7Pd0?= =?us-ascii?Q?CQ8gATAvgvB+Tm6n5aYtH9b3NDmJ8xbrFqoFA6ya?= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(82310400026)(376014)(36860700013)(13003099007); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Dec 2025 09:26:17.1271 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c51ab5db-3358-44d0-b0f6-08de4397a817 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC3.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6442 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 23.11.6 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 12/30/25. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/shanipr/dpdk-stable This queued commit can be viewed at: https://github.com/shanipr/dpdk-stable/commit/b431414c74e2474e9fb5a7677fc4b9d3184c3c3a Thanks. Shani --- >From b431414c74e2474e9fb5a7677fc4b9d3184c3c3a Mon Sep 17 00:00:00 2001 From: Dariusz Sosnowski Date: Fri, 14 Nov 2025 21:17:20 +0100 Subject: [PATCH] net/mlx5: fix flow tag indexes support on root table [ upstream commit 3087db16ab13cdd6996b1f3ea8c64171c2e8fd8f ] Offending patch introduced support for additional flow tag indexes with HW Steering flow engine. New tag indexes will be mapped to HW registers REG_C_8 to REG_C_11, depending on HW capabilities. That patch only handled tables created on group > 0 (non-root table), where mlx5 PMD directly configures the HW. Tables and flow rules on group 0 (root table) are handled through kernel driver, and new registers were not addressed for that case. Because of that, usage of unsupported tag index in group 0 triggered an assertion in flow_dv_match_meta_reg(). This patch adds necessary definitions for REG_C_8 to REG_C_11 to make these registers usable for flow tag indexes in root table. Validation of flow tag to HW register translation is also amended to report invalid cases to the user, instead of relying on assertions. Fixes: 7e3a14423c1a ("net/mlx5/hws: support 4 additional C registers") Signed-off-by: Dariusz Sosnowski --- drivers/common/mlx5/mlx5_prm.h | 6 ++++- drivers/net/mlx5/mlx5_flow_dv.c | 40 ++++++++++++++++++++++++++++----- 2 files changed, 39 insertions(+), 7 deletions(-) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index d9e216b635..64d814d2d3 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1184,7 +1184,11 @@ struct mlx5_ifc_fte_match_set_misc5_bits { u8 tunnel_header_1[0x20]; u8 tunnel_header_2[0x20]; u8 tunnel_header_3[0x20]; - u8 reserved[0x100]; + u8 reserved[0x80]; + u8 metadata_reg_c_8[0x20]; + u8 metadata_reg_c_9[0x20]; + u8 metadata_reg_c_10[0x20]; + u8 metadata_reg_c_11[0x20]; }; /* Flow matcher. */ diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 56a0beeef6..d42b95ce0c 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -10175,8 +10175,8 @@ static void flow_dv_match_meta_reg(void *key, enum modify_reg reg_type, uint32_t data, uint32_t mask) { - void *misc2_v = - MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2); + void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2); + void *misc5_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_5); uint32_t temp; data &= mask; @@ -10220,6 +10220,18 @@ flow_dv_match_meta_reg(void *key, enum modify_reg reg_type, case REG_C_7: MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data); break; + case REG_C_8: + MLX5_SET(fte_match_set_misc5, misc5_v, metadata_reg_c_8, data); + break; + case REG_C_9: + MLX5_SET(fte_match_set_misc5, misc5_v, metadata_reg_c_9, data); + break; + case REG_C_10: + MLX5_SET(fte_match_set_misc5, misc5_v, metadata_reg_c_10, data); + break; + case REG_C_11: + MLX5_SET(fte_match_set_misc5, misc5_v, metadata_reg_c_11, data); + break; default: MLX5_ASSERT(false); break; @@ -10438,8 +10450,11 @@ flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev, void *key, * Flow pattern to translate. * @param[in] key_type * Set flow matcher mask or value. + * + * @return + * 0 on success. Negative errno value otherwise. */ -static void +static int flow_dv_translate_item_tag(struct rte_eth_dev *dev, void *key, const struct rte_flow_item *item, uint32_t key_type) @@ -10451,7 +10466,7 @@ flow_dv_translate_item_tag(struct rte_eth_dev *dev, void *key, uint32_t index; if (MLX5_ITEM_VALID(item, key_type)) - return; + return 0; MLX5_ITEM_UPDATE(item, key_type, tag_v, tag_m, &rte_flow_item_tag_mask); /* When set mask, the index should be from spec. */ @@ -10461,8 +10476,18 @@ flow_dv_translate_item_tag(struct rte_eth_dev *dev, void *key, reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, index, NULL); else reg = flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_TAG, index); - MLX5_ASSERT(reg > 0); + if (reg < 0) { + DRV_LOG(ERR, "port %u tag index %u does not map to correct register", + dev->data->port_id, index); + return -EINVAL; + } + if (reg == REG_NON) { + DRV_LOG(ERR, "port %u tag index %u maps to unsupported register", + dev->data->port_id, index); + return -ENOTSUP; + } flow_dv_match_meta_reg(key, (enum modify_reg)reg, tag_v->data, tag_m->data); + return 0; } /** @@ -13931,7 +13956,10 @@ flow_dv_translate_items(struct rte_eth_dev *dev, last_item = MLX5_FLOW_LAYER_ICMP6; break; case RTE_FLOW_ITEM_TYPE_TAG: - flow_dv_translate_item_tag(dev, key, items, key_type); + ret = flow_dv_translate_item_tag(dev, key, items, key_type); + if (ret < 0) + return rte_flow_error_set(error, -ret, RTE_FLOW_ERROR_TYPE_ITEM, NULL, + "invalid flow tag item"); last_item = MLX5_FLOW_ITEM_TAG; break; case MLX5_RTE_FLOW_ITEM_TYPE_TAG: -- 2.43.0 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2025-12-25 11:16:41.254613292 +0200 +++ 0094-net-mlx5-fix-flow-tag-indexes-support-on-root-table.patch 2025-12-25 11:16:36.303788000 +0200 @@ -1 +1 @@ -From 3087db16ab13cdd6996b1f3ea8c64171c2e8fd8f Mon Sep 17 00:00:00 2001 +From b431414c74e2474e9fb5a7677fc4b9d3184c3c3a Mon Sep 17 00:00:00 2001 @@ -5,0 +6,2 @@ +[ upstream commit 3087db16ab13cdd6996b1f3ea8c64171c2e8fd8f ] + @@ -24 +25,0 @@ -Cc: stable@dpdk.org @@ -29 +29,0 @@ - drivers/net/mlx5/mlx5_flow.h | 3 ++- @@ -31 +31 @@ - 3 files changed, 41 insertions(+), 8 deletions(-) + 2 files changed, 39 insertions(+), 7 deletions(-) @@ -34 +34 @@ -index 6cde3f8f1a..9383e09893 100644 +index d9e216b635..64d814d2d3 100644 @@ -37 +37 @@ -@@ -1205,7 +1205,11 @@ struct mlx5_ifc_fte_match_set_misc5_bits { +@@ -1184,7 +1184,11 @@ struct mlx5_ifc_fte_match_set_misc5_bits { @@ -50,14 +49,0 @@ -diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h -index db408d7b38..8159008504 100644 ---- a/drivers/net/mlx5/mlx5_flow.h -+++ b/drivers/net/mlx5/mlx5_flow.h -@@ -1837,7 +1837,8 @@ flow_hw_get_reg_id_by_domain(struct rte_eth_dev *dev, - case RTE_FLOW_ITEM_TYPE_TAG: - if (id == RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX) - return REG_C_3; -- MLX5_ASSERT(id < MLX5_FLOW_HW_TAGS_MAX); -+ if (id >= MLX5_FLOW_HW_TAGS_MAX) -+ return REG_NON; - return reg->hw_avl_tags[id]; - default: - return REG_NON; @@ -65 +51 @@ -index 83046418c4..47f6d28410 100644 +index 56a0beeef6..d42b95ce0c 100644 @@ -68 +54 @@ -@@ -10554,8 +10554,8 @@ static void +@@ -10175,8 +10175,8 @@ static void @@ -78,2 +64,2 @@ - if (!key) -@@ -10601,6 +10601,18 @@ flow_dv_match_meta_reg(void *key, enum modify_reg reg_type, + data &= mask; +@@ -10220,6 +10220,18 @@ flow_dv_match_meta_reg(void *key, enum modify_reg reg_type, @@ -98 +84 @@ -@@ -10819,8 +10831,11 @@ flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev, void *key, +@@ -10438,8 +10450,11 @@ flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev, void *key, @@ -111 +97 @@ -@@ -10832,7 +10847,7 @@ flow_dv_translate_item_tag(struct rte_eth_dev *dev, void *key, +@@ -10451,7 +10466,7 @@ flow_dv_translate_item_tag(struct rte_eth_dev *dev, void *key, @@ -120 +106 @@ -@@ -10842,8 +10857,18 @@ flow_dv_translate_item_tag(struct rte_eth_dev *dev, void *key, +@@ -10461,8 +10476,18 @@ flow_dv_translate_item_tag(struct rte_eth_dev *dev, void *key, @@ -140 +126 @@ -@@ -14402,7 +14427,10 @@ flow_dv_translate_items(struct rte_eth_dev *dev, +@@ -13931,7 +13956,10 @@ flow_dv_translate_items(struct rte_eth_dev *dev,