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Thu, 25 Dec 2025 01:26:24 -0800 From: Shani Peretz To: Viacheslav Ovsiienko CC: dpdk stable Subject: patch 'net/mlx5: fix flex flow item header length' has been queued to stable release 23.11.6 Date: Thu, 25 Dec 2025 11:19:00 +0200 Message-ID: <20251225091938.345892-99-shperetz@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251225091938.345892-1-shperetz@nvidia.com> References: <20251221145746.763179-93-shperetz@nvidia.com> <20251225091938.345892-1-shperetz@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000FCC4:EE_|LV3PR12MB9093:EE_ X-MS-Office365-Filtering-Correlation-Id: 57f4a39f-e2cd-43e6-0dc6-08de4397b624 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|1800799024|36860700013|376014|13003099007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?b7tfa4aSX0bXgb3WTrR96evLHgUJVRlkGAPnGaw4Iq7TlMvw+oPzKwuIFtFT?= =?us-ascii?Q?GjV0Y+AFdvkrD5ty6Trr0QWQXTtP4z61KvuR6Hj/sLwNOK+2X/1AzJFiVLtV?= =?us-ascii?Q?P8yfGO3NdFCQ+35YnnmSbFtS26UaetfR5Mdh/5qIUtFc/h9IyNeMUzfQSvV6?= =?us-ascii?Q?35OCzuHPDxBPzuTEeM9uAQxm5CZHfRWsOkYoVnilVl8ARw2AnwSwqWS2sJYk?= =?us-ascii?Q?4pO+hsYmI6KKUFhhHpYX06ZmQ/qlbr7P+skKPSRuMkLV+d46/i+OdjLBaoG/?= =?us-ascii?Q?A4fOt5nyjxqDwVVvYDY73aacgufHK97Bb8yyQoR2UvsYxmOjVfLgOxbrgPzs?= =?us-ascii?Q?u7JY7dPCkzr1s/tZXi+aWQrrzHnecgzc7Qy35nlbJb4L1pqLwkbYRultf5/n?= =?us-ascii?Q?0PPlFUfNDby6+camk8Xh31Jdbw2GPup/zNS5ybmpLZ8RTqmuTMU074v4ILCa?= =?us-ascii?Q?H+crfG3Uzy4Z9p9kIALN5G8gvis9ibgw5bfwMgV+keaq1Nb4ovdTPavDTTz2?= =?us-ascii?Q?gWDALAK5QYdZyqEFDKvAJ2xa6N9eJgCXlHmm39HZNF03f89yIH0dqBtjpBaB?= =?us-ascii?Q?tmBqFUmL4FO55AiRxOwobUsXjRtvpJRg60zfmtiT2U21Mzi24TINkNORxmw4?= =?us-ascii?Q?NtH5RHsy3U90aucLlo4/CGZyEYrptCEhgVFtp2OO0VPO8X7LiP8Hq51Zj3p4?= =?us-ascii?Q?fxLEB4y5xcOsSulr1WxFkmWOLVS72cjQVQ5Gf6je7ek/AXASj2gDBVjpQn4v?= =?us-ascii?Q?FXuB1w0tnWbU7NClookeIy91rizgBdo3P7gFtSxDXrOnJUoMJA4cG2SfaDuV?= =?us-ascii?Q?VIUhupa0/47KxxZDrYEFXGabB8hBFA2h3e9S7qArpnnhgcWU+nps+0k7Z2x9?= =?us-ascii?Q?eC4wdMWY9JGs48lK3lGnEEHPwqkONVd1xMYhFnYdNZVSRZE95Z3xCtJvu5s0?= =?us-ascii?Q?PzAb7uVRrfOEaw3qrnk6Rd5Hl5Rbnz2FBCzkFSxtZLXQ0otMtyIftQ+QtFI6?= =?us-ascii?Q?22qM7p/yuRbiJ2+raOdtrSWmaFtcuVRmKJ5pcP9ln4TaxmVLhRSziKg3R1wA?= =?us-ascii?Q?25ewzAkg4QgMannHw+s5UYCKAymj/rUPeIShcUAP3WGbb3OaLt6gh2GAUbFo?= =?us-ascii?Q?OREuBs5Id5E5rNcxg6iBCPAb/zufaJ13NFDMBKVscbIjK0GGBIDwFl13KKYT?= =?us-ascii?Q?Kbh1D5Gn5+l1fk54mIeu+GtMRJFZ5fsMTfhn9UvbeJdNCw8a9wg3YSTvqE04?= =?us-ascii?Q?utQTscaaBC+QfPWK4zohemqECeHE8M1mbqbVCrkrNroNHyGp0/f5Gv/hUJsc?= =?us-ascii?Q?k1kr44387NiuheHCNvLXjVjPRJ5264IU7YCgu9KP/OTtfFXyhHZ1UXIDu/Jr?= =?us-ascii?Q?He/yl74TkFbXXULxYv2rWMe8CktsMydBUMgEYr5jGIwRodzAIocZW4ClwrTz?= =?us-ascii?Q?4MICTMp/uqJ9RgoSiHHex3lBlo3K+OGWMLH4kO7LjB9d6+U4CMWG2tTQwDTi?= =?us-ascii?Q?zcmX0iyhJXFCH7d4IYMPZfq7S1r70OLTDKgfyEHfDLRzoEcCG25m2TugyKjM?= =?us-ascii?Q?zMML4WPu33FOM9zSUoCxwPUl0lvrYvTTYS1uctLJ?= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014)(13003099007); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Dec 2025 09:26:40.6946 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 57f4a39f-e2cd-43e6-0dc6-08de4397b624 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9093 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 23.11.6 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 12/30/25. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/shanipr/dpdk-stable This queued commit can be viewed at: https://github.com/shanipr/dpdk-stable/commit/b513b4052a7b3594a6a10fb6bd5869de7f14b515 Thanks. Shani --- >From b513b4052a7b3594a6a10fb6bd5869de7f14b515 Mon Sep 17 00:00:00 2001 From: Viacheslav Ovsiienko Date: Tue, 18 Nov 2025 16:57:06 +0200 Subject: [PATCH] net/mlx5: fix flex flow item header length [ upstream commit a2234609bf7e4f5bb1ad8f6f60c5f574f32c3558 ] There is the updated firmware providing the new capability bit "header_length_field_offset_mode". If this bit is set the length field offset in flex parser configuration should not be adjusted by the supported field mask left margin, and the bit "header_length_field_offset_mode" should be set in configuration command on the flex parser creation firmware call. Fixes: b04b06f4cb3f ("net/mlx5: fix flex item header length field translation") Signed-off-by: Viacheslav Ovsiienko --- drivers/common/mlx5/mlx5_devx_cmds.c | 4 ++++ drivers/common/mlx5/mlx5_devx_cmds.h | 2 ++ drivers/common/mlx5/mlx5_prm.h | 8 ++++++-- drivers/net/mlx5/mlx5.c | 12 +++++++++--- drivers/net/mlx5/mlx5_flow_flex.c | 3 ++- 5 files changed, 23 insertions(+), 6 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 9e2d7ce86f..e65f15addb 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -741,6 +741,8 @@ mlx5_devx_cmd_create_flex_parser(void *ctx, MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); MLX5_SET(parse_graph_flex, flex, header_length_mode, data->header_length_mode); + MLX5_SET(parse_graph_flex, flex, header_length_field_offset_mode, + data->header_length_field_offset_mode); MLX5_SET64(parse_graph_flex, flex, modify_field_select, data->modify_field_select); MLX5_SET(parse_graph_flex, flex, header_length_base_value, @@ -868,6 +870,8 @@ mlx5_devx_cmd_query_hca_parse_graph_node_cap max_next_header_offset); attr->header_length_mask_width = MLX5_GET(parse_graph_node_cap, hcattr, header_length_mask_width); + attr->header_length_field_mode_wa = !MLX5_GET(parse_graph_node_cap, hcattr, + header_length_field_offset_mode); /* Get the max supported samples from HCA CAP 2 */ hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 028cf2abb9..9ad16d24e1 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -119,6 +119,7 @@ struct mlx5_hca_flex_attr { uint8_t sample_tunnel_inner2:1; uint8_t zero_size_supported:1; uint8_t sample_id_in_out:1; + uint8_t header_length_field_mode_wa:1; uint16_t max_base_header_length; uint8_t max_sample_base_offset; uint16_t max_next_header_offset; @@ -624,6 +625,7 @@ struct mlx5_devx_graph_node_attr { uint32_t header_length_base_value:16; uint32_t header_length_field_shift:4; uint32_t header_length_field_offset:16; + uint32_t header_length_field_offset_mode:1; uint32_t header_length_field_mask; struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM]; uint32_t next_header_field_offset:16; diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 64d814d2d3..a72bc7ab81 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -2089,7 +2089,9 @@ struct mlx5_ifc_parse_graph_node_cap_bits { u8 max_num_arc_in[0x08]; u8 max_num_arc_out[0x08]; u8 max_num_sample[0x08]; - u8 reserved_at_78[0x03]; + u8 reserved_at_78[0x01]; + u8 header_length_field_offset_mode[0x1]; + u8 reserved_at_79[0x01]; u8 parse_graph_anchor[0x1]; u8 reserved_at_7c[0x01]; u8 sample_tunnel_inner2[0x1]; @@ -4836,7 +4838,9 @@ struct mlx5_ifc_parse_graph_flex_bits { u8 next_header_field_offset[0x10]; u8 reserved_at_160[0x12]; u8 head_anchor_id[0x6]; - u8 reserved_at_178[0x3]; + u8 reserved_at_178[0x1]; + u8 header_length_field_offset_mode[0x1]; + u8 reserved_at_17a[0x1]; u8 next_header_field_size[0x5]; u8 header_length_field_mask[0x20]; u8 reserved_at_224[0x20]; diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index 0352e7cc7f..900737e191 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -1090,9 +1090,15 @@ mlx5_alloc_srh_flex_parser(struct rte_eth_dev *dev) /* The unit is uint64_t. */ node.header_length_field_shift = 0x3; /* Header length is the 2nd byte. */ - node.header_length_field_offset = 0x8; - if (attr->header_length_mask_width < 8) - node.header_length_field_offset += 8 - attr->header_length_mask_width; + if (attr->header_length_field_mode_wa) { + /* Legacy firmware before ConnectX-8, we should provide offset WA. */ + node.header_length_field_offset = 8; + if (attr->header_length_mask_width < 8) + node.header_length_field_offset += 8 - attr->header_length_mask_width; + } else { + /* The new firmware, we can specify the correct offset directly. */ + node.header_length_field_offset = 12; + } node.header_length_field_mask = 0xF; /* One byte next header protocol. */ node.next_header_field_size = 0x8; diff --git a/drivers/net/mlx5/mlx5_flow_flex.c b/drivers/net/mlx5/mlx5_flow_flex.c index 58d8c61443..8de2174173 100644 --- a/drivers/net/mlx5/mlx5_flow_flex.c +++ b/drivers/net/mlx5/mlx5_flow_flex.c @@ -554,7 +554,7 @@ mlx5_flex_translate_length(struct mlx5_hca_flex_attr *attr, "mask and shift combination not supported (OFFSET)"); msb++; offset += field->field_size - msb; - if (msb < attr->header_length_mask_width) { + if (attr->header_length_field_mode_wa && msb < attr->header_length_mask_width) { if (attr->header_length_mask_width - msb > offset) return rte_flow_error_set (error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, NULL, @@ -572,6 +572,7 @@ mlx5_flex_translate_length(struct mlx5_hca_flex_attr *attr, node->header_length_field_mask = mask; node->header_length_field_shift = shift; node->header_length_field_offset = offset; + node->header_length_field_offset_mode = !attr->header_length_field_mode_wa; break; } case FIELD_MODE_BITMASK: -- 2.43.0 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2025-12-25 11:16:41.513439885 +0200 +++ 0099-net-mlx5-fix-flex-flow-item-header-length.patch 2025-12-25 11:16:36.356790000 +0200 @@ -1 +1 @@ -From a2234609bf7e4f5bb1ad8f6f60c5f574f32c3558 Mon Sep 17 00:00:00 2001 +From b513b4052a7b3594a6a10fb6bd5869de7f14b515 Mon Sep 17 00:00:00 2001 @@ -5,0 +6,2 @@ +[ upstream commit a2234609bf7e4f5bb1ad8f6f60c5f574f32c3558 ] + @@ -15 +16,0 @@ -Cc: stable@dpdk.org @@ -27 +28 @@ -index 22f6b29089..d12ebf8487 100644 +index 9e2d7ce86f..e65f15addb 100644 @@ -30 +31 @@ -@@ -784,6 +784,8 @@ mlx5_devx_cmd_create_flex_parser(void *ctx, +@@ -741,6 +741,8 @@ mlx5_devx_cmd_create_flex_parser(void *ctx, @@ -39 +40 @@ -@@ -911,6 +913,8 @@ mlx5_devx_cmd_query_hca_parse_graph_node_cap +@@ -868,6 +870,8 @@ mlx5_devx_cmd_query_hca_parse_graph_node_cap @@ -49 +50 @@ -index 4c7747cbec..da50fc686c 100644 +index 028cf2abb9..9ad16d24e1 100644 @@ -60 +61 @@ -@@ -654,6 +655,7 @@ struct mlx5_devx_graph_node_attr { +@@ -624,6 +625,7 @@ struct mlx5_devx_graph_node_attr { @@ -69 +70 @@ -index 9383e09893..ba33336e58 100644 +index 64d814d2d3..a72bc7ab81 100644 @@ -72 +73 @@ -@@ -2119,7 +2119,9 @@ struct mlx5_ifc_parse_graph_node_cap_bits { +@@ -2089,7 +2089,9 @@ struct mlx5_ifc_parse_graph_node_cap_bits { @@ -83 +84 @@ -@@ -4991,7 +4993,9 @@ struct mlx5_ifc_parse_graph_flex_bits { +@@ -4836,7 +4838,9 @@ struct mlx5_ifc_parse_graph_flex_bits { @@ -95 +96 @@ -index 447fd31fd4..c1cfcb1f67 100644 +index 0352e7cc7f..900737e191 100644 @@ -98 +99 @@ -@@ -1080,9 +1080,15 @@ mlx5_alloc_srh_flex_parser(struct rte_eth_dev *dev) +@@ -1090,9 +1090,15 @@ mlx5_alloc_srh_flex_parser(struct rte_eth_dev *dev) @@ -118 +119 @@ -index b1174fe0ed..d21e28f7fd 100644 +index 58d8c61443..8de2174173 100644