[dpdk-stable] [PATCH] examples/l3fwd: fix unaligned memory access

[dpdk-stable] [PATCH] examples/l3fwd: fix unaligned memory access

[hgovindh]

Fix unaligned memory access when reading IPv6 header which
leads to segmentation fault by changing aligned memory read
to unaligned memory read.

Bugzilla ID: 279
Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build")
Cc: maciej.czekaj@caviumnetworks.com
Cc: stable@dpdk.org
Signed-off-by: hgovindh <hariprasad.govindharajan@intel.com>
---
 examples/l3fwd/l3fwd_em.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
index fa8f82be6..f0c443dae 100644
--- a/examples/l3fwd/l3fwd_em.c
+++ b/examples/l3fwd/l3fwd_em.c
@@ -285,7 +285,7 @@ em_get_ipv6_dst_port(void *ipv6_hdr, uint16_t portid, void *lookup_struct)
 	 * Get part of 5 tuple: dst IP address lower 96 bits
 	 * and src IP address higher 32 bits.
 	 */
-	key.xmm[1] = *(xmm_t *)data1;
+	key.xmm[1] = _mm_loadu_si128((xmm_t *)data1);
 
 	/*
 	 * Get part of 5 tuple: dst port and src port
-- 
2.22.0

Re: [dpdk-stable] [dpdk-dev] [PATCH] examples/l3fwd: fix unaligned memory access

[Ruifeng Wang (Arm Technology China)]

Hi,

> -----Original Message-----
> From: dev <dev-bounces@dpdk.org> On Behalf Of hgovindh
> Sent: Thursday, July 25, 2019 00:44
> To: Remy Horton <remy.horton@intel.com>; Marko Kovacevic
> <marko.kovacevic@intel.com>; Ori Kam <orika@mellanox.com>; Bruce
> Richardson <bruce.richardson@intel.com>; Pablo de Lara
> <pablo.de.lara.guarch@intel.com>; Radu Nicolau <radu.nicolau@intel.com>;
> Akhil.goyal@nxp.com; Tomasz Kantecki <tomasz.kantecki@intel.com>
> Cc: dev@dpdk.org; hgovindh <hariprasad.govindharajan@intel.com>;
> maciej.czekaj@caviumnetworks.com; stable@dpdk.org
> Subject: [dpdk-dev] [PATCH] examples/l3fwd: fix unaligned memory access
> 
> Fix unaligned memory access when reading IPv6 header which leads to
> segmentation fault by changing aligned memory read to unaligned memory
> read.
> 
> Bugzilla ID: 279
> Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build")
> Cc: maciej.czekaj@caviumnetworks.com
> Cc: stable@dpdk.org
> Signed-off-by: hgovindh <hariprasad.govindharajan@intel.com>
> ---
>  examples/l3fwd/l3fwd_em.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
> index fa8f82be6..f0c443dae 100644
> --- a/examples/l3fwd/l3fwd_em.c
> +++ b/examples/l3fwd/l3fwd_em.c
> @@ -285,7 +285,7 @@ em_get_ipv6_dst_port(void *ipv6_hdr, uint16_t
> portid, void *lookup_struct)
>  	 * Get part of 5 tuple: dst IP address lower 96 bits
>  	 * and src IP address higher 32 bits.
>  	 */
> -	key.xmm[1] = *(xmm_t *)data1;
> +	key.xmm[1] = _mm_loadu_si128((xmm_t *)data1);

The use of SSE intrinsics on general path will break build on other architectures.
How about use em_mask_key() instead?
> 
>  	/*
>  	 * Get part of 5 tuple: dst port and src port
> --
> 2.22.0

Re: [dpdk-stable] [PATCH] examples/l3fwd: fix unaligned memory access

[Bruce Richardson]

On Wed, Jul 24, 2019 at 05:43:54PM +0100, hgovindh wrote:
> Fix unaligned memory access when reading IPv6 header which
> leads to segmentation fault by changing aligned memory read
> to unaligned memory read.
> 
> Bugzilla ID: 279
> Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build")
> Cc: maciej.czekaj@caviumnetworks.com
> Cc: stable@dpdk.org
> Signed-off-by: hgovindh <hariprasad.govindharajan@intel.com>
> ---
>  examples/l3fwd/l3fwd_em.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
> index fa8f82be6..f0c443dae 100644
> --- a/examples/l3fwd/l3fwd_em.c
> +++ b/examples/l3fwd/l3fwd_em.c
> @@ -285,7 +285,7 @@ em_get_ipv6_dst_port(void *ipv6_hdr, uint16_t portid, void *lookup_struct)
>  	 * Get part of 5 tuple: dst IP address lower 96 bits
>  	 * and src IP address higher 32 bits.
>  	 */
> -	key.xmm[1] = *(xmm_t *)data1;
> +	key.xmm[1] = _mm_loadu_si128((xmm_t *)data1);
>  

Minor nit, but since data1 is defined as "void *" the cast to xmm_t is
unnecessary.

Although we can't reproduce the bug, the fix looks correct for the bug as
described and harmless otherwise, so:

Acked-by: Bruce Richardson <bruce.richardson@intel.com>

Re: [dpdk-stable] [dpdk-dev] [PATCH] examples/l3fwd: fix unaligned memory access

[Aaron Conole]

hgovindh <hariprasad.govindharajan@intel.com> writes:

> Fix unaligned memory access when reading IPv6 header which
> leads to segmentation fault by changing aligned memory read
> to unaligned memory read.
>
> Bugzilla ID: 279
> Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build")
> Cc: maciej.czekaj@caviumnetworks.com
> Cc: stable@dpdk.org
> Signed-off-by: hgovindh <hariprasad.govindharajan@intel.com>
> ---
>  examples/l3fwd/l3fwd_em.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
> index fa8f82be6..f0c443dae 100644
> --- a/examples/l3fwd/l3fwd_em.c
> +++ b/examples/l3fwd/l3fwd_em.c
> @@ -285,7 +285,7 @@ em_get_ipv6_dst_port(void *ipv6_hdr, uint16_t portid, void *lookup_struct)
>  	 * Get part of 5 tuple: dst IP address lower 96 bits
>  	 * and src IP address higher 32 bits.
>  	 */
> -	key.xmm[1] = *(xmm_t *)data1;
> +	key.xmm[1] = _mm_loadu_si128((xmm_t *)data1);

Nak.  Please use a generic unaligned load, rather than an intel specific
one.  Otherwise, supported platforms like arm64 will have broken builds.

Additionally, which chip and compiler did you use to get this error?

>  
>  	/*
>  	 * Get part of 5 tuple: dst port and src port

Re: [dpdk-stable] [dpdk-dev] [PATCH] examples/l3fwd: fix unaligned memory access

[Burakov, Anatoly]

On 25-Jul-19 2:27 PM, Aaron Conole wrote:
> hgovindh <hariprasad.govindharajan@intel.com> writes:
> 
>> Fix unaligned memory access when reading IPv6 header which
>> leads to segmentation fault by changing aligned memory read
>> to unaligned memory read.
>>
>> Bugzilla ID: 279
>> Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build")
>> Cc: maciej.czekaj@caviumnetworks.com
>> Cc: stable@dpdk.org
>> Signed-off-by: hgovindh <hariprasad.govindharajan@intel.com>
>> ---
>>   examples/l3fwd/l3fwd_em.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
>> index fa8f82be6..f0c443dae 100644
>> --- a/examples/l3fwd/l3fwd_em.c
>> +++ b/examples/l3fwd/l3fwd_em.c
>> @@ -285,7 +285,7 @@ em_get_ipv6_dst_port(void *ipv6_hdr, uint16_t portid, void *lookup_struct)
>>   	 * Get part of 5 tuple: dst IP address lower 96 bits
>>   	 * and src IP address higher 32 bits.
>>   	 */
>> -	key.xmm[1] = *(xmm_t *)data1;
>> +	key.xmm[1] = _mm_loadu_si128((xmm_t *)data1);
> 
> Nak.  Please use a generic unaligned load, rather than an intel specific
> one.  Otherwise, supported platforms like arm64 will have broken builds.
> 
> Additionally, which chip and compiler did you use to get this error?

I have reproduced this error on Intel Xeon E5-2699 and GCC 7.4 (Ubuntu 
18.04).

> 
>>   
>>   	/*
>>   	 * Get part of 5 tuple: dst port and src port
> 


-- 
Thanks,
Anatoly

Re: [dpdk-stable] [dpdk-dev] [PATCH] examples/l3fwd: fix unaligned memory access

[Lipiec, Herakliusz]

> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Aaron Conole
> Sent: Thursday, July 25, 2019 2:28 PM
> hgovindh <hariprasad.govindharajan@intel.com> writes:
> 
> > Fix unaligned memory access when reading IPv6 header which leads to
> > segmentation fault by changing aligned memory read to unaligned memory
> > read.
> >
> > Bugzilla ID: 279
> > Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build")
> > Cc: maciej.czekaj@caviumnetworks.com
> > Cc: stable@dpdk.org
> > Signed-off-by: hgovindh <hariprasad.govindharajan@intel.com>
> > ---
> >  examples/l3fwd/l3fwd_em.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
> > index fa8f82be6..f0c443dae 100644
> > --- a/examples/l3fwd/l3fwd_em.c
> > +++ b/examples/l3fwd/l3fwd_em.c
> > @@ -285,7 +285,7 @@ em_get_ipv6_dst_port(void *ipv6_hdr, uint16_t
> portid, void *lookup_struct)
> >  	 * Get part of 5 tuple: dst IP address lower 96 bits
> >  	 * and src IP address higher 32 bits.
> >  	 */
> > -	key.xmm[1] = *(xmm_t *)data1;
> > +	key.xmm[1] = _mm_loadu_si128((xmm_t *)data1);
> 
> Nak.  Please use a generic unaligned load, rather than an intel specific one.
> Otherwise, supported platforms like arm64 will have broken builds.
> 
> Additionally, which chip and compiler did you use to get this error?
This comes from Bugzilla, the compiler used there is GCC 8.2.0 and the CPU is Intel Core i5,
As far as I know this can also be reproduced on Intel Xeon, with GCC 8.3.0, 
in both cases its compiled with compiler optimizations disabled.
> 
> >
> >  	/*
> >  	 * Get part of 5 tuple: dst port and src port

Re: [dpdk-stable] [dpdk-dev] [PATCH] examples/l3fwd: fix unaligned memory access

[Govindharajan, Hariprasad]

-----Original Message-----
From: Burakov, Anatoly 
Sent: Thursday, July 25, 2019 3:01 PM
To: Aaron Conole <aconole@redhat.com>; Govindharajan, Hariprasad <hariprasad.govindharajan@intel.com>
Cc: Remy Horton <remy.horton@intel.com>; Kovacevic, Marko <marko.kovacevic@intel.com>; Ori Kam <orika@mellanox.com>; Richardson, Bruce <bruce.richardson@intel.com>; De Lara Guarch, Pablo <pablo.de.lara.guarch@intel.com>; Nicolau, Radu <radu.nicolau@intel.com>; Akhil Goyal <akhil.goyal@nxp.com>; Kantecki, Tomasz <tomasz.kantecki@intel.com>; dev@dpdk.org; stable@dpdk.org
Subject: Re: [dpdk-dev] [PATCH] examples/l3fwd: fix unaligned memory access

On 25-Jul-19 2:27 PM, Aaron Conole wrote:
> hgovindh <hariprasad.govindharajan@intel.com> writes:
> 
>> Fix unaligned memory access when reading IPv6 header which leads to 
>> segmentation fault by changing aligned memory read to unaligned 
>> memory read.
>>
>> Bugzilla ID: 279
>> Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build")
>> Cc: maciej.czekaj@caviumnetworks.com
>> Cc: stable@dpdk.org
>> Signed-off-by: hgovindh <hariprasad.govindharajan@intel.com>
>> ---
>>   examples/l3fwd/l3fwd_em.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c 
>> index fa8f82be6..f0c443dae 100644
>> --- a/examples/l3fwd/l3fwd_em.c
>> +++ b/examples/l3fwd/l3fwd_em.c
>> @@ -285,7 +285,7 @@ em_get_ipv6_dst_port(void *ipv6_hdr, uint16_t portid, void *lookup_struct)
>>   	 * Get part of 5 tuple: dst IP address lower 96 bits
>>   	 * and src IP address higher 32 bits.
>>   	 */
>> -	key.xmm[1] = *(xmm_t *)data1;
>> +	key.xmm[1] = _mm_loadu_si128((xmm_t *)data1);
> 
> Nak.  Please use a generic unaligned load, rather than an intel 
> specific one.  Otherwise, supported platforms like arm64 will have broken builds.
> 
> Additionally, which chip and compiler did you use to get this error?

I have reproduced this error on Intel Xeon E5-2699 and GCC 7.4 (Ubuntu 18.04).

I have reproduced this error on Intel(R) Xeon(R) CPU and GCC 8.3.0 (Ubuntu 16.04).
> 
>>   
>>   	/*
>>   	 * Get part of 5 tuple: dst port and src port
> 


--
Thanks,
G Hariprasad

Re: [dpdk-stable] [dpdk-dev] [PATCH] examples/l3fwd: fix unaligned memory access

[Burakov, Anatoly]

On 25-Jul-19 3:01 PM, Lipiec, Herakliusz wrote:
> 
> 
>> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Aaron Conole
>> Sent: Thursday, July 25, 2019 2:28 PM
>> hgovindh <hariprasad.govindharajan@intel.com> writes:
>>
>>> Fix unaligned memory access when reading IPv6 header which leads to
>>> segmentation fault by changing aligned memory read to unaligned memory
>>> read.
>>>
>>> Bugzilla ID: 279
>>> Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build")
>>> Cc: maciej.czekaj@caviumnetworks.com
>>> Cc: stable@dpdk.org
>>> Signed-off-by: hgovindh <hariprasad.govindharajan@intel.com>
>>> ---
>>>   examples/l3fwd/l3fwd_em.c | 2 +-
>>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
>>> index fa8f82be6..f0c443dae 100644
>>> --- a/examples/l3fwd/l3fwd_em.c
>>> +++ b/examples/l3fwd/l3fwd_em.c
>>> @@ -285,7 +285,7 @@ em_get_ipv6_dst_port(void *ipv6_hdr, uint16_t
>> portid, void *lookup_struct)
>>>   	 * Get part of 5 tuple: dst IP address lower 96 bits
>>>   	 * and src IP address higher 32 bits.
>>>   	 */
>>> -	key.xmm[1] = *(xmm_t *)data1;
>>> +	key.xmm[1] = _mm_loadu_si128((xmm_t *)data1);
>>
>> Nak.  Please use a generic unaligned load, rather than an intel specific one.
>> Otherwise, supported platforms like arm64 will have broken builds.
>>
>> Additionally, which chip and compiler did you use to get this error?
> This comes from Bugzilla, the compiler used there is GCC 8.2.0 and the CPU is Intel Core i5,
> As far as I know this can also be reproduced on Intel Xeon, with GCC 8.3.0,
> in both cases its compiled with compiler optimizations disabled.

I have reproduced it with compiler optimizations enabled as well.

>>
>>>
>>>   	/*
>>>   	 * Get part of 5 tuple: dst port and src port
> 


-- 
Thanks,
Anatoly

[dpdk-stable] [PATCH v2] examples/l3fwd: fix unaligned memory access

[hgovindh]

Fix unaligned memory access when reading IPv6 header which
leads to segmentation fault by changing aligned memory read
to unaligned memory read.

Bugzilla ID: 279
Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build")
Cc: maciej.czekaj@caviumnetworks.com
Cc: stable@dpdk.org
Signed-off-by: hgovindh <hariprasad.govindharajan@intel.com>
---
V2: Added functions which will do unaligned load based on the
underlying architecture
---
---
 examples/l3fwd/l3fwd_em.c | 26 ++++++++++++++++++++++++--
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
index fa8f82be6..f2641586b 100644
--- a/examples/l3fwd/l3fwd_em.c
+++ b/examples/l3fwd/l3fwd_em.c
@@ -244,6 +244,29 @@ em_mask_key(void *key, xmm_t mask)
 #error No vector engine (SSE, NEON, ALTIVEC) available, check your toolchain
 #endif
 
+#if defined(RTE_MACHINE_CPUFLAG_SSE2)
+static inline xmm_t
+em_load_key(void *key)
+{
+	return _mm_loadu_si128((__m128i *)(key));
+}
+#elif defined(RTE_MACHINE_CPUFLAG_NEON)
+static inline xmm_t
+em_load_key(void *key)
+{
+	return vld1q_s32((int32_t *)key);
+}
+#elif defined(RTE_MACHINE_CPUFLAG_ALTIVEC)
+static inline xmm_t
+em_load_key(void *key)
+{
+	return vec_ld(0, (xmm_t *)(key));
+}
+#else
+#error No vector engine (SSE, NEON, ALTIVEC) available, check your toolchain
+#endif
+
+
 static inline uint16_t
 em_get_ipv4_dst_port(void *ipv4_hdr, uint16_t portid, void *lookup_struct)
 {
@@ -285,8 +308,7 @@ em_get_ipv6_dst_port(void *ipv6_hdr, uint16_t portid, void *lookup_struct)
 	 * Get part of 5 tuple: dst IP address lower 96 bits
 	 * and src IP address higher 32 bits.
 	 */
-	key.xmm[1] = *(xmm_t *)data1;
-
+	key.xmm[1] = em_load_key(data1);
 	/*
 	 * Get part of 5 tuple: dst port and src port
 	 * and dst IP address higher 32 bits.
-- 
2.22.0

Re: [dpdk-stable] [PATCH v2] examples/l3fwd: fix unaligned memory access

[Bruce Richardson]

On Thu, Jul 25, 2019 at 05:29:03PM +0100, hgovindh wrote:
> Fix unaligned memory access when reading IPv6 header which
> leads to segmentation fault by changing aligned memory read
> to unaligned memory read.
> 
> Bugzilla ID: 279
> Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build")
> Cc: maciej.czekaj@caviumnetworks.com
> Cc: stable@dpdk.org
> Signed-off-by: hgovindh <hariprasad.govindharajan@intel.com>
> ---
> V2: Added functions which will do unaligned load based on the
> underlying architecture
> ---
> ---
>  examples/l3fwd/l3fwd_em.c | 26 ++++++++++++++++++++++++--
>  1 file changed, 24 insertions(+), 2 deletions(-)
> 
> diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
> index fa8f82be6..f2641586b 100644
> --- a/examples/l3fwd/l3fwd_em.c
> +++ b/examples/l3fwd/l3fwd_em.c
> @@ -244,6 +244,29 @@ em_mask_key(void *key, xmm_t mask)
>  #error No vector engine (SSE, NEON, ALTIVEC) available, check your toolchain
>  #endif
>  
> +#if defined(RTE_MACHINE_CPUFLAG_SSE2)
> +static inline xmm_t
> +em_load_key(void *key)
> +{
> +	return _mm_loadu_si128((__m128i *)(key));
> +}
> +#elif defined(RTE_MACHINE_CPUFLAG_NEON)
> +static inline xmm_t
> +em_load_key(void *key)
> +{
> +	return vld1q_s32((int32_t *)key);
> +}
> +#elif defined(RTE_MACHINE_CPUFLAG_ALTIVEC)
> +static inline xmm_t
> +em_load_key(void *key)
> +{
> +	return vec_ld(0, (xmm_t *)(key));
> +}

Two minor nits:

Since you are passing in a void *, no typecasts should be needed in any of
these functions.

Also, is it neater if you just have the ifdefs in the middle of the
function, rather than duplicating the function prototype each time? Third
option is to make the load a single-line macro rather than 5-lines of a
function.

/Bruce

Re: [dpdk-stable] [dpdk-dev] [PATCH v2] examples/l3fwd: fix unaligned memory access

[Jerin Jacob Kollanukkaran]

> -----Original Message-----
> From: dev <dev-bounces@dpdk.org> On Behalf Of Bruce Richardson
> Sent: Thursday, July 25, 2019 10:16 PM
> To: hgovindh <hariprasad.govindharajan@intel.com>
> Cc: Remy Horton <remy.horton@intel.com>; Marko Kovacevic
> <marko.kovacevic@intel.com>; Ori Kam <orika@mellanox.com>; Pablo de
> Lara <pablo.de.lara.guarch@intel.com>; Radu Nicolau
> <radu.nicolau@intel.com>; Akhil Goyal <akhil.goyal@nxp.com>; Tomasz
> Kantecki <tomasz.kantecki@intel.com>; dev@dpdk.org;
> maciej.czekaj@caviumnetworks.com; stable@dpdk.org
> Subject: Re: [dpdk-dev] [PATCH v2] examples/l3fwd: fix unaligned memory
> access
> 
> On Thu, Jul 25, 2019 at 05:29:03PM +0100, hgovindh wrote:
> > Fix unaligned memory access when reading IPv6 header which leads to
> > segmentation fault by changing aligned memory read to unaligned memory
> > read.
> >
> > Bugzilla ID: 279
> > Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build")
> > Cc: maciej.czekaj@caviumnetworks.com
> > Cc: stable@dpdk.org
> > Signed-off-by: hgovindh <hariprasad.govindharajan@intel.com>
> > ---
> > V2: Added functions which will do unaligned load based on the
> > underlying architecture
> > ---
> > ---
> >  examples/l3fwd/l3fwd_em.c | 26 ++++++++++++++++++++++++--
> >  1 file changed, 24 insertions(+), 2 deletions(-)
> >
> > diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
> > index fa8f82be6..f2641586b 100644
> > --- a/examples/l3fwd/l3fwd_em.c
> > +++ b/examples/l3fwd/l3fwd_em.c
> > @@ -244,6 +244,29 @@ em_mask_key(void *key, xmm_t mask)  #error No
> > vector engine (SSE, NEON, ALTIVEC) available, check your toolchain
> > #endif
> >
> > +#if defined(RTE_MACHINE_CPUFLAG_SSE2) static inline xmm_t
> > +em_load_key(void *key) {
> > +	return _mm_loadu_si128((__m128i *)(key)); } #elif
> > +defined(RTE_MACHINE_CPUFLAG_NEON)
> > +static inline xmm_t
> > +em_load_key(void *key)
> > +{
> > +	return vld1q_s32((int32_t *)key);
> > +}
> > +#elif defined(RTE_MACHINE_CPUFLAG_ALTIVEC)
> > +static inline xmm_t
> > +em_load_key(void *key)
> > +{
> > +	return vec_ld(0, (xmm_t *)(key));
> > +}

Added power pc maintainer

Not sure all architecture need SIMD instructions for access to unaligned memory location.

@hgovindh,
Could you provide exact setup details for reproducing this issue, I can test it on arm64.
Like l3fwd command, Traffic generator traffic pattern

Re: [dpdk-stable] [dpdk-dev] [PATCH v2] examples/l3fwd: fix unaligned memory access

[David Christensen]

>> On Thu, Jul 25, 2019 at 05:29:03PM +0100, hgovindh wrote:
>>> Fix unaligned memory access when reading IPv6 header which leads to
>>> segmentation fault by changing aligned memory read to unaligned memory
>>> read.
>>>
>>> Bugzilla ID: 279
>>> Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build")
>>> Cc: maciej.czekaj@caviumnetworks.com
>>> Cc: stable@dpdk.org
>>> Signed-off-by: hgovindh <hariprasad.govindharajan@intel.com>
>>> ---
>>> V2: Added functions which will do unaligned load based on the
>>> underlying architecture
>>> ---
>>> ---
>>>   examples/l3fwd/l3fwd_em.c | 26 ++++++++++++++++++++++++--
>>>   1 file changed, 24 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
>>> index fa8f82be6..f2641586b 100644
>>> --- a/examples/l3fwd/l3fwd_em.c
>>> +++ b/examples/l3fwd/l3fwd_em.c
>>> @@ -244,6 +244,29 @@ em_mask_key(void *key, xmm_t mask)  #error No
>>> vector engine (SSE, NEON, ALTIVEC) available, check your toolchain
>>> #endif
>>>
>>> +#if defined(RTE_MACHINE_CPUFLAG_SSE2) static inline xmm_t
>>> +em_load_key(void *key) {
>>> +	return _mm_loadu_si128((__m128i *)(key)); } #elif
>>> +defined(RTE_MACHINE_CPUFLAG_NEON)
>>> +static inline xmm_t
>>> +em_load_key(void *key)
>>> +{
>>> +	return vld1q_s32((int32_t *)key);
>>> +}
>>> +#elif defined(RTE_MACHINE_CPUFLAG_ALTIVEC)
>>> +static inline xmm_t
>>> +em_load_key(void *key)
>>> +{
>>> +	return vec_ld(0, (xmm_t *)(key));
>>> +}
> 
> Added power pc maintainer

> Not sure all architecture need SIMD instructions for access to unaligned memory location.
> 
> @hgovindh,
> Could you provide exact setup details for reproducing this issue, I can test it on arm64.
> Like l3fwd command, Traffic generator traffic pattern

The vec_ld() function requires 16 byte alignment.  (My understanding is 
that GCC code will mask the lower four bits of the address to enforce 
the requirement: 
https://gcc.gcc.gnu.narkive.com/cJndcMpR/vec-ld-versus-vec-vsx-ld-on-power8) 
  Power 8 and later processors support the vec_vsx_ld() function which 
does not have the same memory alignment requirements.

I'll need to try and reproduce the original bug to see what code is 
actually being generated.  Outside of vector instructions I wouldn't 
expect to see errors with unaligned data references.

Dave

Re: [dpdk-stable] [dpdk-dev] [PATCH v2] examples/l3fwd: fix unaligned memory access

[David Christensen]

>>>> Fix unaligned memory access when reading IPv6 header which leads to
>>>> segmentation fault by changing aligned memory read to unaligned memory
>>>> read.
>>>>
>>>> Bugzilla ID: 279
>>>> Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build")
>>>> Cc: maciej.czekaj@caviumnetworks.com
>>>> Cc: stable@dpdk.org
>>>> Signed-off-by: hgovindh <hariprasad.govindharajan@intel.com>
>>>> ---
>>>> V2: Added functions which will do unaligned load based on the
>>>> underlying architecture
>>>> ---
>>>> ---
>>>>   examples/l3fwd/l3fwd_em.c | 26 ++++++++++++++++++++++++--
>>>>   1 file changed, 24 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
>>>> index fa8f82be6..f2641586b 100644
>>>> --- a/examples/l3fwd/l3fwd_em.c
>>>> +++ b/examples/l3fwd/l3fwd_em.c
>>>> @@ -244,6 +244,29 @@ em_mask_key(void *key, xmm_t mask)  #error No
>>>> vector engine (SSE, NEON, ALTIVEC) available, check your toolchain
>>>> #endif
>>>>
>>>> +#if defined(RTE_MACHINE_CPUFLAG_SSE2) static inline xmm_t
>>>> +em_load_key(void *key) {
>>>> +    return _mm_loadu_si128((__m128i *)(key)); } #elif
>>>> +defined(RTE_MACHINE_CPUFLAG_NEON)
>>>> +static inline xmm_t
>>>> +em_load_key(void *key)
>>>> +{
>>>> +    return vld1q_s32((int32_t *)key);
>>>> +}
>>>> +#elif defined(RTE_MACHINE_CPUFLAG_ALTIVEC)
>>>> +static inline xmm_t
>>>> +em_load_key(void *key)
>>>> +{
>>>> +    return vec_ld(0, (xmm_t *)(key));
>>>> +}
>>
>> Added power pc maintainer
> 
>> Not sure all architecture need SIMD instructions for access to 
>> unaligned memory location.
>>
>> @hgovindh,
>> Could you provide exact setup details for reproducing this issue, I 
>> can test it on arm64.
>> Like l3fwd command, Traffic generator traffic pattern
> 
> The vec_ld() function requires 16 byte alignment.  (My understanding is 
> that GCC code will mask the lower four bits of the address to enforce 
> the requirement: 
> https://gcc.gcc.gnu.narkive.com/cJndcMpR/vec-ld-versus-vec-vsx-ld-on-power8) 
>   Power 8 and later processors support the vec_vsx_ld() function which 
> does not have the same memory alignment requirements.
> 
> I'll need to try and reproduce the original bug to see what code is 
> actually being generated.  Outside of vector instructions I wouldn't 
> expect to see errors with unaligned data references.

Tested original bugzilla 279 on Power 9 system with RHEL 7.6 and gcc 
4.8.5, no segmentation fault observed after 30 minutes (observed 
segmentation fault on Intel system immediately).

Code dissassembly:
(gdb) info line l3fwd_em.c:290
Line 290 of "/home/davec/src/dpdk/examples/l3fwd/l3fwd_em.c" starts at 
address 0x10146fbc <em_main_loop+1660>
    and ends at 0x10146fc0 <em_main_loop+1664>.
(gdb) disass /m 0x10146fbc,0x10146fc0
Dump of assembler code from 0x10146fbc to 0x10146fc0:
290		key.xmm[1] = *(xmm_t *)data1;
    0x0000000010146fbc <em_main_loop+1660>:	li      r7,20

End of assembler dump.

Since vector element ordering is different on Intel vs Power/ARM, 
suggest only applying vector operation to Intel code at this time 
otherwise additional steps may be required to modify MASK values to 
match the new vector operations.

Dave

Re: [dpdk-stable] [EXT] Re: [dpdk-dev] [PATCH v2] examples/l3fwd: fix unaligned memory access

[Jerin Jacob Kollanukkaran]

> -----Original Message-----
> From: David Christensen <drc@linux.vnet.ibm.com>
> Sent: Friday, July 26, 2019 3:36 AM
> To: Jerin Jacob Kollanukkaran <jerinj@marvell.com>; Bruce Richardson
> <bruce.richardson@intel.com>; hgovindh
> <hariprasad.govindharajan@intel.com>
> Cc: Remy Horton <remy.horton@intel.com>; Marko Kovacevic
> <marko.kovacevic@intel.com>; Ori Kam <orika@mellanox.com>; Pablo de
> Lara <pablo.de.lara.guarch@intel.com>; Radu Nicolau
> <radu.nicolau@intel.com>; Akhil Goyal <akhil.goyal@nxp.com>; Tomasz
> Kantecki <tomasz.kantecki@intel.com>; dev@dpdk.org;
> maciej.czekaj@caviumnetworks.com; stable@dpdk.org; Gavin Hu
> <gavin.hu@arm.com>
> Subject: [EXT] Re: [dpdk-dev] [PATCH v2] examples/l3fwd: fix unaligned
> memory access
> 
> 
>>>> Fix unaligned memory access when reading IPv6 header which leads to
> >>>> segmentation fault by changing aligned memory read to unaligned
> >>>> memory read.
> >>>>
> >>>> Bugzilla ID: 279
> >>>> Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build")
> >>>> Cc: maciej.czekaj@caviumnetworks.com
> >>>> Cc: stable@dpdk.org
> >>>> Signed-off-by: hgovindh <hariprasad.govindharajan@intel.com>
> >>>> ---
> >>>> V2: Added functions which will do unaligned load based on the
> >>>> underlying architecture
> >>>> ---
> >>>> ---
> >>>>   examples/l3fwd/l3fwd_em.c | 26 ++++++++++++++++++++++++--
> >>>>   1 file changed, 24 insertions(+), 2 deletions(-)
> >>>>
> >>>> diff --git a/examples/l3fwd/l3fwd_em.c
> b/examples/l3fwd/l3fwd_em.c
> >>>> index fa8f82be6..f2641586b 100644
> >>>> --- a/examples/l3fwd/l3fwd_em.c
> >>>> +++ b/examples/l3fwd/l3fwd_em.c
> >>>> @@ -244,6 +244,29 @@ em_mask_key(void *key, xmm_t
> mask)  #error No
> >>>> vector engine (SSE, NEON, ALTIVEC) available, check your toolchain
> >>>> #endif
> >>>>
> >>>> +#if defined(RTE_MACHINE_CPUFLAG_SSE2) static inline xmm_t
> >>>> +em_load_key(void *key) {
> >>>> +    return _mm_loadu_si128((__m128i *)(key)); } #elif
> >>>> +defined(RTE_MACHINE_CPUFLAG_NEON)
> >>>> +static inline xmm_t
> >>>> +em_load_key(void *key)
> >>>> +{
> >>>> +    return vld1q_s32((int32_t *)key); } #elif
> >>>> +defined(RTE_MACHINE_CPUFLAG_ALTIVEC)
> >>>> +static inline xmm_t
> >>>> +em_load_key(void *key)
> >>>> +{
> >>>> +    return vec_ld(0, (xmm_t *)(key)); }
> >>
> >> Added power pc maintainer
> >
> >> Not sure all architecture need SIMD instructions for access to
> >> unaligned memory location.
> >>
> >> @hgovindh,
> >> Could you provide exact setup details for reproducing this issue, I
> >> can test it on arm64.
> >> Like l3fwd command, Traffic generator traffic pattern
> >
> > The vec_ld() function requires 16 byte alignment.  (My understanding
> > is that GCC code will mask the lower four bits of the address to
> > enforce the requirement:
> > https://gcc.gcc.gnu.narkive.com/cJndcMpR/vec-ld-versus-vec-vsx-ld-on-p
> > ower8)
> >   Power 8 and later processors support the vec_vsx_ld() function which
> > does not have the same memory alignment requirements.
> >
> > I'll need to try and reproduce the original bug to see what code is
> > actually being generated.  Outside of vector instructions I wouldn't
> > expect to see errors with unaligned data references.
> 
> Tested original bugzilla 279 on Power 9 system with RHEL 7.6 and gcc 4.8.5, no
> segmentation fault observed after 30 minutes (observed segmentation fault
> on Intel system immediately).
> 
> Code dissassembly:
> (gdb) info line l3fwd_em.c:290
> Line 290 of "/home/davec/src/dpdk/examples/l3fwd/l3fwd_em.c" starts at
> address 0x10146fbc <em_main_loop+1660>
>     and ends at 0x10146fc0 <em_main_loop+1664>.
> (gdb) disass /m 0x10146fbc,0x10146fc0
> Dump of assembler code from 0x10146fbc to 0x10146fc0:
> 290		key.xmm[1] = *(xmm_t *)data1;
>     0x0000000010146fbc <em_main_loop+1660>:	li      r7,20
> 
> End of assembler dump.
> 
> Since vector element ordering is different on Intel vs Power/ARM, suggest
> only applying vector operation to Intel code at this time otherwise additional
> steps may be required to modify MASK values to match the new vector
> operations.

On arm64, Generated assembly is following. Where LDUR and STR works
With unaligned memory(i.e no need for special handling).
I would suggest to have eal function to abstract The difference between x86 vs Power/ARM
to avoid ifdef clutter in all the applications.

             key.xmm[1] = *(xmm_t *)data1;
   0x00000000004ebed4 <+1188>:  60 40 c1 3c     ldur    q0, [x3, #20]
   0x00000000004ebedc <+1196>:  a0 73 80 3d     str     q0, [x29, #448]
   0x00000000004ec064 <+1588>:  41 40 c1 3c     ldur    q1, [x2, #20]
   0x00000000004ec06c <+1596>:  a1 73 80 3d     str     q1, [x29, #448]

> 
> Dave

[dpdk-stable] [PATCH v3] examples/l3fwd: fix unaligned memory access

[hgovindh]

Fix unaligned memory access when reading IPv6 header which
leads to segmentation fault by changing aligned memory read
to unaligned memory read.

Bugzilla ID: 279
Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build")
Cc: maciej.czekaj@caviumnetworks.com
Cc: stable@dpdk.org
Signed-off-by: hgovindh <hariprasad.govindharajan@intel.com>
---
V2: Added functions which will do unaligned load based on the
underlying architecture

V3: Removed functions added in V2 and replaced them with if macros
which will branch based on the underlying architecture. As per my
understanding since the unaligned load affects only Intel arch,
I added that function branch and left the original code for other arc.
Can someone with ARM and PowerPC arch, could you please validate this
patch and let me know?
---
 examples/l3fwd/l3fwd_em.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
index 5f499e005..ea9ca9491 100644
--- a/examples/l3fwd/l3fwd_em.c
+++ b/examples/l3fwd/l3fwd_em.c
@@ -244,6 +244,7 @@ em_mask_key(void *key, xmm_t mask)
 #error No vector engine (SSE, NEON, ALTIVEC) available, check your toolchain
 #endif
 
+
 static inline uint16_t
 em_get_ipv4_dst_port(void *ipv4_hdr, uint16_t portid, void *lookup_struct)
 {
@@ -287,8 +288,11 @@ em_get_ipv6_dst_port(void *ipv6_hdr, uint16_t portid, void *lookup_struct)
 	 * Get part of 5 tuple: dst IP address lower 96 bits
 	 * and src IP address higher 32 bits.
 	 */
+#if defined RTE_ARCH_X86
+	key.xmm[1] = _mm_loadu_si128(data1);
+#else
 	key.xmm[1] = *(xmm_t *)data1;
-
+#endif
 	/*
 	 * Get part of 5 tuple: dst port and src port
 	 * and dst IP address higher 32 bits.
-- 
2.22.0

Re: [dpdk-stable] [dpdk-dev] [PATCH v3] examples/l3fwd: fix unaligned memory access

[Burakov, Anatoly]

On 26-Jul-19 2:27 PM, hgovindh wrote:
> Fix unaligned memory access when reading IPv6 header which
> leads to segmentation fault by changing aligned memory read
> to unaligned memory read.
> 
> Bugzilla ID: 279
> Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build")
> Cc: maciej.czekaj@caviumnetworks.com
> Cc: stable@dpdk.org
> Signed-off-by: hgovindh <hariprasad.govindharajan@intel.com>
> ---
> V2: Added functions which will do unaligned load based on the
> underlying architecture
> 
> V3: Removed functions added in V2 and replaced them with if macros
> which will branch based on the underlying architecture. As per my
> understanding since the unaligned load affects only Intel arch,
> I added that function branch and left the original code for other arc.
> Can someone with ARM and PowerPC arch, could you please validate this
> patch and let me know?
> ---
>   examples/l3fwd/l3fwd_em.c | 6 +++++-
>   1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
> index 5f499e005..ea9ca9491 100644
> --- a/examples/l3fwd/l3fwd_em.c
> +++ b/examples/l3fwd/l3fwd_em.c
> @@ -244,6 +244,7 @@ em_mask_key(void *key, xmm_t mask)
>   #error No vector engine (SSE, NEON, ALTIVEC) available, check your toolchain
>   #endif
>   
> +
>   static inline uint16_t

Unintended whitespace change?

-- 
Thanks,
Anatoly

[dpdk-stable] [PATCH v4] examples/l3fwd: fix unaligned memory access

[hgovindh]

Fix unaligned memory access when reading IPv6 header which
leads to segmentation fault by changing aligned memory read
to unaligned memory read.

Bugzilla ID: 279
Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build")
Cc: maciej.czekaj@caviumnetworks.com
Cc: stable@dpdk.org
Signed-off-by: hgovindh <hariprasad.govindharajan@intel.com>
---
V2: Added functions which will do unaligned load based on the
underlying architecture

V3: Removed functions added in V2 and replaced them with if macros
which will branch based on the underlying architecture. As per my
understanding since the unaligned load affects only Intel arch,
I added that function branch and left the original code for other arc.
Can someone with ARM and PowerPC arch, could you please validate this
patch and let me know?
---
 examples/l3fwd/l3fwd_em.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
index 5f499e005..ad6fe76e8 100644
--- a/examples/l3fwd/l3fwd_em.c
+++ b/examples/l3fwd/l3fwd_em.c
@@ -287,8 +287,11 @@ em_get_ipv6_dst_port(void *ipv6_hdr, uint16_t portid, void *lookup_struct)
 	 * Get part of 5 tuple: dst IP address lower 96 bits
 	 * and src IP address higher 32 bits.
 	 */
+#if defined RTE_ARCH_X86
+	key.xmm[1] = _mm_loadu_si128(data1);
+#else
 	key.xmm[1] = *(xmm_t *)data1;
-
+#endif
 	/*
 	 * Get part of 5 tuple: dst port and src port
 	 * and dst IP address higher 32 bits.
-- 
2.22.0

Re: [dpdk-stable] [PATCH v4] examples/l3fwd: fix unaligned memory access

[Thomas Monjalon]

Review please?

26/07/2019 15:58, hgovindh:
> Fix unaligned memory access when reading IPv6 header which
> leads to segmentation fault by changing aligned memory read
> to unaligned memory read.
> 
> Bugzilla ID: 279
> Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build")
> Cc: maciej.czekaj@caviumnetworks.com
> Cc: stable@dpdk.org
> Signed-off-by: hgovindh <hariprasad.govindharajan@intel.com>
> --- a/examples/l3fwd/l3fwd_em.c
> +++ b/examples/l3fwd/l3fwd_em.c
> +#if defined RTE_ARCH_X86
> +	key.xmm[1] = _mm_loadu_si128(data1);
> +#else
>  	key.xmm[1] = *(xmm_t *)data1;
> -
> +#endif

Re: [dpdk-stable] [PATCH v4] examples/l3fwd: fix unaligned memory access

[Bruce Richardson]

On Tue, Jul 30, 2019 at 10:50:14AM +0200, Thomas Monjalon wrote:
> Review please?
> 
> 26/07/2019 15:58, hgovindh:
> > Fix unaligned memory access when reading IPv6 header which
> > leads to segmentation fault by changing aligned memory read
> > to unaligned memory read.
> > 
> > Bugzilla ID: 279
> > Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build")
> > Cc: maciej.czekaj@caviumnetworks.com
> > Cc: stable@dpdk.org
> > Signed-off-by: hgovindh <hariprasad.govindharajan@intel.com>
> > --- a/examples/l3fwd/l3fwd_em.c
> > +++ b/examples/l3fwd/l3fwd_em.c
> > +#if defined RTE_ARCH_X86
> > +	key.xmm[1] = _mm_loadu_si128(data1);
> > +#else
> >  	key.xmm[1] = *(xmm_t *)data1;
> > -
> > +#endif
> 

The blank line should be re-added below the #ifdef. Apart from that the fix
looks correct to me.

Reviewed-by: Bruce Richardson <bruce.richardson@intel.com>

Re: [dpdk-stable] [dpdk-dev] [PATCH v4] examples/l3fwd: fix unaligned memory access

[Jerin Jacob Kollanukkaran]

> -----Original Message-----
> From: dev <dev-bounces@dpdk.org> On Behalf Of Bruce Richardson
> Sent: Tuesday, July 30, 2019 3:17 PM
> To: Thomas Monjalon <thomas@monjalon.net>
> Cc: dev@dpdk.org; stable@dpdk.org; hgovindh
> <hariprasad.govindharajan@intel.com>; Marko Kovacevic
> <marko.kovacevic@intel.com>; Ori Kam <orika@mellanox.com>; Pablo de Lara
> <pablo.de.lara.guarch@intel.com>; Radu Nicolau <radu.nicolau@intel.com>;
> Akhil Goyal <akhil.goyal@nxp.com>; Tomasz Kantecki
> <tomasz.kantecki@intel.com>; drc@linux.vnet.ibm.com;
> ruifeng.wang@arm.com; maciej.czekaj@caviumnetworks.com
> Subject: Re: [dpdk-dev] [dpdk-stable] [PATCH v4] examples/l3fwd: fix unaligned
> memory access
> 
> On Tue, Jul 30, 2019 at 10:50:14AM +0200, Thomas Monjalon wrote:
> > Review please?
> >
> > 26/07/2019 15:58, hgovindh:
> > > Fix unaligned memory access when reading IPv6 header which leads to
> > > segmentation fault by changing aligned memory read to unaligned
> > > memory read.
> > >
> > > Bugzilla ID: 279
> > > Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build")
> > > Cc: maciej.czekaj@caviumnetworks.com
> > > Cc: stable@dpdk.org
> > > Signed-off-by: hgovindh <hariprasad.govindharajan@intel.com>
> > > --- a/examples/l3fwd/l3fwd_em.c
> > > +++ b/examples/l3fwd/l3fwd_em.c
> > > +#if defined RTE_ARCH_X86
> > > +	key.xmm[1] = _mm_loadu_si128(data1); #else
> > >  	key.xmm[1] = *(xmm_t *)data1;
> > > -
> > > +#endif
> >
> 
> The blank line should be re-added below the #ifdef. Apart from that the fix looks
> correct to me.
> 
> Reviewed-by: Bruce Richardson <bruce.richardson@intel.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>

[dpdk-stable] [PATCH v5] Examples/l3fwd: fix unaligned memory access

[Hariprasad Govindharajan]

Fix unaligned memory access when reading IPv6 header which
leads to segmentation fault by changing aligned memory read
to unaligned memory read.

Bugzilla ID: 279
Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build")
Cc: maciej.czekaj@caviumnetworks.com
Cc: stable@dpdk.org
Signed-off-by: Hariprasad Govindharajan <hariprasad.govindharajan@intel.com>
Reviewed-by: Bruce Richardson <bruce.richardson@intel.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
V2: Added functions which will do unaligned load based on the
underlying architecture

V3: Removed functions added in V2 and replaced them with if macros
which will branch based on the underlying architecture. As per my
understanding since the unaligned load affects only Intel arch,
I added that function branch and left the original code for other arc.
Can someone with ARM and PowerPC arch, could you please validate this
patch and let me know?

V5: Fixed coding style issues.
---
 examples/l3fwd/l3fwd_em.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
index 5f499e005..74a7c8fa4 100644
--- a/examples/l3fwd/l3fwd_em.c
+++ b/examples/l3fwd/l3fwd_em.c
@@ -287,7 +287,11 @@ em_get_ipv6_dst_port(void *ipv6_hdr, uint16_t portid, void *lookup_struct)
 	 * Get part of 5 tuple: dst IP address lower 96 bits
 	 * and src IP address higher 32 bits.
 	 */
+#if defined RTE_ARCH_X86
+	key.xmm[1] = _mm_loadu_si128(data1);
+#else
 	key.xmm[1] = *(xmm_t *)data1;
+#endif
 
 	/*
 	 * Get part of 5 tuple: dst port and src port
-- 
2.22.0

Re: [dpdk-stable] [dpdk-dev] [PATCH v5] Examples/l3fwd: fix unaligned memory access

[Lipiec, Herakliusz]

> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Hariprasad
> Govindharajan
> 
> Fix unaligned memory access when reading IPv6 header which leads to
> segmentation fault by changing aligned memory read to unaligned memory
> read.
> 
> Bugzilla ID: 279
> Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build")
> Cc: maciej.czekaj@caviumnetworks.com
> Cc: stable@dpdk.org
> Signed-off-by: Hariprasad Govindharajan
> <hariprasad.govindharajan@intel.com>
> Reviewed-by: Bruce Richardson <bruce.richardson@intel.com>
> Reviewed-by: Jerin Jacob <jerinj@marvell.com>
> ---

Tested-by: Herakliusz Lipiec <herakliusz.lipiec@intel.com>
Reviewed-by: Herakliusz Lipiec <herakliusz.lipiec@intel.com>

Re: [dpdk-stable] [dpdk-dev] [PATCH v4] examples/l3fwd: fix unaligned memory access

[David Christensen]

>> On Tue, Jul 30, 2019 at 10:50:14AM +0200, Thomas Monjalon wrote:
>>> Review please?
>>>
>>> 26/07/2019 15:58, hgovindh:
>>>> Fix unaligned memory access when reading IPv6 header which leads to
>>>> segmentation fault by changing aligned memory read to unaligned
>>>> memory read.
>>>>
>>>> Bugzilla ID: 279
>>>> Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build")
>>>> Cc: maciej.czekaj@caviumnetworks.com
>>>> Cc: stable@dpdk.org
>>>> Signed-off-by: hgovindh <hariprasad.govindharajan@intel.com>
>>>> --- a/examples/l3fwd/l3fwd_em.c
>>>> +++ b/examples/l3fwd/l3fwd_em.c
>>>> +#if defined RTE_ARCH_X86
>>>> +	key.xmm[1] = _mm_loadu_si128(data1); #else
>>>>   	key.xmm[1] = *(xmm_t *)data1;
>>>> -
>>>> +#endif
>>>
>>
>> The blank line should be re-added below the #ifdef. Apart from that the fix looks
>> correct to me.
>>
>> Reviewed-by: Bruce Richardson <bruce.richardson@intel.com>
> Reviewed-by: Jerin Jacob <jerinj@marvell.com>
Reviewed-by: David Christensen <drc@linux.vnet.ibm.com>

Re: [dpdk-stable] [dpdk-dev] [PATCH v5] Examples/l3fwd: fix unaligned memory access

[Thomas Monjalon]

30/07/2019 17:48, Lipiec, Herakliusz:
> > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Hariprasad
> > Govindharajan
> > 
> > Fix unaligned memory access when reading IPv6 header which leads to
> > segmentation fault by changing aligned memory read to unaligned memory
> > read.
> > 
> > Bugzilla ID: 279
> > Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build")
> > Cc: maciej.czekaj@caviumnetworks.com
> > Cc: stable@dpdk.org
> > Signed-off-by: Hariprasad Govindharajan
> > <hariprasad.govindharajan@intel.com>
> > Reviewed-by: Bruce Richardson <bruce.richardson@intel.com>
> > Reviewed-by: Jerin Jacob <jerinj@marvell.com>
> 
> Tested-by: Herakliusz Lipiec <herakliusz.lipiec@intel.com>
> Reviewed-by: Herakliusz Lipiec <herakliusz.lipiec@intel.com>

Applied, thanks

Re: [dpdk-stable] [dpdk-dev] [PATCH v4] examples/l3fwd: fix unaligned memory access

[Ruifeng Wang (Arm Technology China)]

> -----Original Message-----
> From: David Christensen <drc@linux.vnet.ibm.com>
> Sent: Wednesday, July 31, 2019 01:45
> To: jerinj@marvell.com; Bruce Richardson <bruce.richardson@intel.com>;
> thomas@monjalon.net
> Cc: dev@dpdk.org; stable@dpdk.org; hgovindh
> <hariprasad.govindharajan@intel.com>; Marko Kovacevic
> <marko.kovacevic@intel.com>; Ori Kam <orika@mellanox.com>; Pablo de
> Lara <pablo.de.lara.guarch@intel.com>; Radu Nicolau
> <radu.nicolau@intel.com>; Akhil.goyal@nxp.com; Tomasz Kantecki
> <tomasz.kantecki@intel.com>; Ruifeng Wang (Arm Technology China)
> <Ruifeng.Wang@arm.com>; maciej.czekaj@caviumnetworks.com
> Subject: Re: [dpdk-dev] [dpdk-stable] [PATCH v4] examples/l3fwd: fix
> unaligned memory access
> 
> >> On Tue, Jul 30, 2019 at 10:50:14AM +0200, Thomas Monjalon wrote:
> >>> Review please?
> >>>
> >>> 26/07/2019 15:58, hgovindh:
> >>>> Fix unaligned memory access when reading IPv6 header which leads to
> >>>> segmentation fault by changing aligned memory read to unaligned
> >>>> memory read.
> >>>>
> >>>> Bugzilla ID: 279
> >>>> Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build")
> >>>> Cc: maciej.czekaj@caviumnetworks.com
> >>>> Cc: stable@dpdk.org
> >>>> Signed-off-by: hgovindh <hariprasad.govindharajan@intel.com>
> >>>> --- a/examples/l3fwd/l3fwd_em.c
> >>>> +++ b/examples/l3fwd/l3fwd_em.c
> >>>> +#if defined RTE_ARCH_X86
> >>>> +	key.xmm[1] = _mm_loadu_si128(data1); #else
> >>>>   	key.xmm[1] = *(xmm_t *)data1;
> >>>> -
> >>>> +#endif
> >>>
> >>
> >> The blank line should be re-added below the #ifdef. Apart from that
> >> the fix looks correct to me.
> >>
> >> Reviewed-by: Bruce Richardson <bruce.richardson@intel.com>
> > Reviewed-by: Jerin Jacob <jerinj@marvell.com>
> Reviewed-by: David Christensen <drc@linux.vnet.ibm.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>