From: Thomas Monjalon <thomas@monjalon.net>
To: Bing Zhao <bingz@nvidia.com>
Cc: viacheslavo@nvidia.com, matan@nvidia.com, dev@dpdk.org,
rasland@nvidia.com, stable@dpdk.org, akozyrev@nvidia.com
Subject: Re: [dpdk-stable] [dpdk-dev] [PATCH] net/mlx5: fix Tx metadata endianness in data path
Date: Wed, 29 Sep 2021 23:31:57 +0200 [thread overview]
Message-ID: <2545808.iCvCU3XZGg@thomas> (raw)
In-Reply-To: <20210927080203.23877-1-bingz@nvidia.com>
27/09/2021 10:02, Bing Zhao:
> The metadata can be set in the mbuf dynamic field and then used in
> flow rules steering for egress direction. The hardware requires
> network order for both the insertion of a rule and sending a packet.
> Indeed, there is no strict restriction for the endianness. The order
> for sending a packet and its steering rule should be consistent.
>
> In the past, there was no endianness conversion due to the
> performance reason. The flow rule converted the metadata into little
> endian for hardware (if needed) and the packet hit the flow rule also
> with little endian.
>
> After the metadata was converted to big endian, the missing adaption
> in the data path resulted in a flow miss of the egress packets.
>
> Converting the metadata to big endian before posting a WQE to the
> hardware solves this issue.
>
> Fixes: b57e414b48c0 ("net/mlx5: convert meta register to big-endian")
> Cc: akozyrev@nvidia.com
> Cc: stable@dpdk.org
>
> Signed-off-by: Bing Zhao <bingz@nvidia.com>
> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Applied in next-net-mlx, thanks.
prev parent reply other threads:[~2021-09-29 21:32 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-27 8:02 [dpdk-stable] " Bing Zhao
2021-09-29 21:31 ` Thomas Monjalon [this message]
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