From: Xiaoyun wang <cloud.wangxiaoyun@huawei.com>
To: <luobin9@huawei.com>
Cc: Xiaoyun wang <cloud.wangxiaoyun@huawei.com>, <stable@dpdk.org>
Subject: [dpdk-stable] [PATCH v1 2/4] net/hinic: optimize Rx performance for x86
Date: Sat, 25 Jul 2020 11:27:06 +0800 [thread overview]
Message-ID: <826341f78f584d4d779d8cfab5a5e4aa12fb1d0a.1595646109.git.cloud.wangxiaoyun@huawei.com> (raw)
In-Reply-To: <cover.1595646109.git.cloud.wangxiaoyun@huawei.com>
For x86 platform, the rq cqe without cache aligned, which can
improve performace for some gateway scenario.
Fixes: 361a9ccf81d6 ("net/hinic: optimize Rx performance")
Cc: stable@dpdk.org
Signed-off-by: Xiaoyun wang <cloud.wangxiaoyun@huawei.com>
---
drivers/net/hinic/hinic_pmd_rx.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/net/hinic/hinic_pmd_rx.h b/drivers/net/hinic/hinic_pmd_rx.h
index 49fa565..8a45f2d 100644
--- a/drivers/net/hinic/hinic_pmd_rx.h
+++ b/drivers/net/hinic/hinic_pmd_rx.h
@@ -35,7 +35,11 @@ struct hinic_rq_cqe {
u32 rss_hash;
u32 rsvd[4];
+#if defined(RTE_ARCH_ARM64)
} __rte_cache_aligned;
+#else
+};
+#endif
struct hinic_rq_cqe_sect {
struct hinic_sge sge;
--
1.8.3.1
next parent reply other threads:[~2020-07-25 2:59 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <cover.1595646109.git.cloud.wangxiaoyun@huawei.com>
2020-07-25 3:27 ` Xiaoyun wang [this message]
2020-07-25 3:27 ` [dpdk-stable] [PATCH v1 4/4] net/hinic/base: make timeout not affected by system time jump Xiaoyun wang
[not found] <cover.1595648149.git.cloud.wangxiaoyun@huawei.com>
2020-07-25 3:48 ` [dpdk-stable] [PATCH v1 2/4] net/hinic: optimize Rx performance for x86 Xiaoyun wang
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