From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id E7C06A0527 for ; Sat, 25 Jul 2020 04:59:46 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D69641C02D; Sat, 25 Jul 2020 04:59:46 +0200 (CEST) Received: from huawei.com (szxga06-in.huawei.com [45.249.212.32]) by dpdk.org (Postfix) with ESMTP id B9C331C029 for ; Sat, 25 Jul 2020 04:59:44 +0200 (CEST) Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 7BB5D2D21E941708BDD1 for ; Sat, 25 Jul 2020 10:59:33 +0800 (CST) Received: from tester.localdomain (10.175.119.39) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Sat, 25 Jul 2020 10:59:23 +0800 From: Xiaoyun wang To: CC: Xiaoyun wang , Date: Sat, 25 Jul 2020 11:27:06 +0800 Message-ID: <826341f78f584d4d779d8cfab5a5e4aa12fb1d0a.1595646109.git.cloud.wangxiaoyun@huawei.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.175.119.39] X-CFilter-Loop: Reflected Subject: [dpdk-stable] [PATCH v1 2/4] net/hinic: optimize Rx performance for x86 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" For x86 platform, the rq cqe without cache aligned, which can improve performace for some gateway scenario. Fixes: 361a9ccf81d6 ("net/hinic: optimize Rx performance") Cc: stable@dpdk.org Signed-off-by: Xiaoyun wang --- drivers/net/hinic/hinic_pmd_rx.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/hinic/hinic_pmd_rx.h b/drivers/net/hinic/hinic_pmd_rx.h index 49fa565..8a45f2d 100644 --- a/drivers/net/hinic/hinic_pmd_rx.h +++ b/drivers/net/hinic/hinic_pmd_rx.h @@ -35,7 +35,11 @@ struct hinic_rq_cqe { u32 rss_hash; u32 rsvd[4]; +#if defined(RTE_ARCH_ARM64) } __rte_cache_aligned; +#else +}; +#endif struct hinic_rq_cqe_sect { struct hinic_sge sge; -- 1.8.3.1