From: "Wu, Jingjing" <jingjing.wu@intel.com>
To: "Li, Xiaoyun" <xiaoyun.li@intel.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>, "stable@dpdk.org" <stable@dpdk.org>
Subject: Re: [dpdk-stable] [PATCH] raw/ntb: fix write memory barrier issue
Date: Thu, 26 Dec 2019 01:46:54 +0000 [thread overview]
Message-ID: <9BB6961774997848B5B42BEC655768F8115C8E0D@SHSMSX103.ccr.corp.intel.com> (raw)
In-Reply-To: <20191204151916.12607-1-xiaoyun.li@intel.com>
> -----Original Message-----
> From: Li, Xiaoyun <xiaoyun.li@intel.com>
> Sent: Wednesday, December 4, 2019 11:19 PM
> To: Wu, Jingjing <jingjing.wu@intel.com>
> Cc: dev@dpdk.org; Li, Xiaoyun <xiaoyun.li@intel.com>; stable@dpdk.org
> Subject: [PATCH] raw/ntb: fix write memory barrier issue
>
> All buffers and ring info should be written before tail register update.
> This patch relocates the write memory barrier before updating tail register
> to avoid potential issues.
>
> Fixes: 11b5c7daf019 ("raw/ntb: add enqueue and dequeue functions")
> Cc: stable@dpdk.org
>
> Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com>
Acked-by: Jingjing Wu <jingjing.wu@intel.com>
next prev parent reply other threads:[~2019-12-26 1:47 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-04 15:19 Xiaoyun Li
2019-12-14 15:29 ` [dpdk-stable] [dpdk-dev] " Gavin Hu (Arm Technology China)
2019-12-16 1:57 ` Li, Xiaoyun
2019-12-25 3:52 ` Gavin Hu
2019-12-16 1:58 ` [dpdk-stable] [PATCH v2] " Xiaoyun Li
2019-12-16 10:49 ` [dpdk-stable] [dpdk-dev] " Gavin Hu (Arm Technology China)
2019-12-23 7:52 ` Li, Xiaoyun
2019-12-23 8:38 ` Gavin Hu
2019-12-23 9:35 ` Li, Xiaoyun
2019-12-24 15:46 ` Gavin Hu
2019-12-23 2:38 ` [dpdk-stable] " Wu, Jingjing
2019-12-26 1:46 ` Wu, Jingjing [this message]
2020-01-20 9:04 ` [dpdk-stable] [dpdk-dev] [PATCH] " Thomas Monjalon
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