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* [dpdk-stable] [PATCH] net/mlx5: fix metadata item endianness conversion
@ 2019-12-24 14:20 Viacheslav Ovsiienko
  2020-01-06 14:44 ` Matan Azrad
                   ` (2 more replies)
  0 siblings, 3 replies; 5+ messages in thread
From: Viacheslav Ovsiienko @ 2019-12-24 14:20 UTC (permalink / raw)
  To: dev; +Cc: matan, rasland, orika, stable

The metadata register c0 field in the matcher might be split
into two independent fields - the source vport index and META
item value. These fields have no permanent assigned bits, the
configuration is queried from the kernel drivers.

It means the metadata item field might be less than 32 bits.
Also, the metadata are engaged in datapath and there are no
any metadata endianness conversions in datapath to provide the
better performance, all conversions are implemented in rte_flow
engine. If there are less than 32 bits of metadata the extra
right shift is needed after endianness conversion for little-
endian hosts.

Fixes: acfcd5c52f94 ("net/mlx5: update meta register matcher set")
Cc: stable@dpdk.org

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
---
 drivers/net/mlx5/mlx5_flow_dv.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index f8e153c..cb416ca 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -5903,8 +5903,12 @@ struct field_modify_info modify_tcp[] = {
 			struct mlx5_priv *priv = dev->data->dev_private;
 			uint32_t msk_c0 = priv->sh->dv_regc0_mask;
 			uint32_t shl_c0 = rte_bsf32(msk_c0);
+#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
+			uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
 
-			msk_c0 = rte_cpu_to_be_32(msk_c0);
+			value >>= shr_c0;
+			mask >>= shr_c0;
+#endif
 			value <<= shl_c0;
 			mask <<= shl_c0;
 			assert(msk_c0);
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [dpdk-stable] [PATCH] net/mlx5: fix metadata item endianness conversion
  2019-12-24 14:20 [dpdk-stable] [PATCH] net/mlx5: fix metadata item endianness conversion Viacheslav Ovsiienko
@ 2020-01-06 14:44 ` Matan Azrad
  2020-01-08  9:03 ` Raslan Darawsheh
  2020-01-17 14:59 ` [dpdk-stable] [PATCH v2] " Viacheslav Ovsiienko
  2 siblings, 0 replies; 5+ messages in thread
From: Matan Azrad @ 2020-01-06 14:44 UTC (permalink / raw)
  To: Slava Ovsiienko, dev; +Cc: Raslan Darawsheh, Ori Kam, stable



From: Viacheslav Ovsiienko
> The metadata register c0 field in the matcher might be split into two
> independent fields - the source vport index and META item value. These
> fields have no permanent assigned bits, the configuration is queried from the
> kernel drivers.
> 
> It means the metadata item field might be less than 32 bits.
> Also, the metadata are engaged in datapath and there are no any metadata
> endianness conversions in datapath to provide the better performance, all
> conversions are implemented in rte_flow engine. If there are less than 32
> bits of metadata the extra right shift is needed after endianness conversion
> for little- endian hosts.
> 
> Fixes: acfcd5c52f94 ("net/mlx5: update meta register matcher set")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [dpdk-stable] [PATCH] net/mlx5: fix metadata item endianness conversion
  2019-12-24 14:20 [dpdk-stable] [PATCH] net/mlx5: fix metadata item endianness conversion Viacheslav Ovsiienko
  2020-01-06 14:44 ` Matan Azrad
@ 2020-01-08  9:03 ` Raslan Darawsheh
  2020-01-17 14:59 ` [dpdk-stable] [PATCH v2] " Viacheslav Ovsiienko
  2 siblings, 0 replies; 5+ messages in thread
From: Raslan Darawsheh @ 2020-01-08  9:03 UTC (permalink / raw)
  To: Slava Ovsiienko, dev; +Cc: Matan Azrad, Ori Kam, stable

Hi,

> -----Original Message-----
> From: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
> Sent: Tuesday, December 24, 2019 4:21 PM
> To: dev@dpdk.org
> Cc: Matan Azrad <matan@mellanox.com>; Raslan Darawsheh
> <rasland@mellanox.com>; Ori Kam <orika@mellanox.com>;
> stable@dpdk.org
> Subject: [PATCH] net/mlx5: fix metadata item endianness conversion
> 
> The metadata register c0 field in the matcher might be split into two
> independent fields - the source vport index and META item value. These
> fields have no permanent assigned bits, the configuration is queried from the
> kernel drivers.
> 
> It means the metadata item field might be less than 32 bits.
> Also, the metadata are engaged in datapath and there are no any metadata
> endianness conversions in datapath to provide the better performance, all
> conversions are implemented in rte_flow engine. If there are less than 32
> bits of metadata the extra right shift is needed after endianness conversion
> for little- endian hosts.
> 
> Fixes: acfcd5c52f94 ("net/mlx5: update meta register matcher set")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
> ---
>  drivers/net/mlx5/mlx5_flow_dv.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/net/mlx5/mlx5_flow_dv.c
> b/drivers/net/mlx5/mlx5_flow_dv.c index f8e153c..cb416ca 100644
> --- a/drivers/net/mlx5/mlx5_flow_dv.c
> +++ b/drivers/net/mlx5/mlx5_flow_dv.c
> @@ -5903,8 +5903,12 @@ struct field_modify_info modify_tcp[] = {
>  			struct mlx5_priv *priv = dev->data->dev_private;
>  			uint32_t msk_c0 = priv->sh->dv_regc0_mask;
>  			uint32_t shl_c0 = rte_bsf32(msk_c0);
> +#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
> +			uint32_t shr_c0 = __builtin_clz(priv->sh-
> >dv_meta_mask);
> 
> -			msk_c0 = rte_cpu_to_be_32(msk_c0);
> +			value >>= shr_c0;
> +			mask >>= shr_c0;
> +#endif
>  			value <<= shl_c0;
>  			mask <<= shl_c0;
>  			assert(msk_c0);
> --
> 1.8.3.1


Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [dpdk-stable] [PATCH v2] net/mlx5: fix metadata item endianness conversion
  2019-12-24 14:20 [dpdk-stable] [PATCH] net/mlx5: fix metadata item endianness conversion Viacheslav Ovsiienko
  2020-01-06 14:44 ` Matan Azrad
  2020-01-08  9:03 ` Raslan Darawsheh
@ 2020-01-17 14:59 ` " Viacheslav Ovsiienko
  2020-01-17 17:19   ` Ferruh Yigit
  2 siblings, 1 reply; 5+ messages in thread
From: Viacheslav Ovsiienko @ 2020-01-17 14:59 UTC (permalink / raw)
  To: dev; +Cc: matan, rasland, ferruh.yigit, stable

The mlx5 datapath does not implement any endianness conversions
for the metadata being sent and received to provide the better
performance (because these conversions would be performed for
each packet). These metadata are also involved into flow processing
(there might be some flows matching on metadata patterns or setting
the new metadata values) inside the NIC. It order to configure
hardware in correct way all necessary endianness conversions are
done by rte_flow handling code (only once on flow creation). This
patch fixes one of these conversions for the little-endian hosts
in case if META/MARK items are less than 32 bits.

Fixes: acfcd5c52f94 ("net/mlx5: update meta register matcher set")
Cc: stable@dpdk.org

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
---
v1: - http://patchwork.dpdk.org/patch/64125/
v2: - commit message is rewritten

 drivers/net/mlx5/mlx5_flow_dv.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index dd21bc6..e8a764c 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -5909,8 +5909,12 @@ struct field_modify_info modify_tcp[] = {
 			struct mlx5_priv *priv = dev->data->dev_private;
 			uint32_t msk_c0 = priv->sh->dv_regc0_mask;
 			uint32_t shl_c0 = rte_bsf32(msk_c0);
+#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
+			uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
 
-			msk_c0 = rte_cpu_to_be_32(msk_c0);
+			value >>= shr_c0;
+			mask >>= shr_c0;
+#endif
 			value <<= shl_c0;
 			mask <<= shl_c0;
 			assert(msk_c0);
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [dpdk-stable] [PATCH v2] net/mlx5: fix metadata item endianness conversion
  2020-01-17 14:59 ` [dpdk-stable] [PATCH v2] " Viacheslav Ovsiienko
@ 2020-01-17 17:19   ` Ferruh Yigit
  0 siblings, 0 replies; 5+ messages in thread
From: Ferruh Yigit @ 2020-01-17 17:19 UTC (permalink / raw)
  To: Viacheslav Ovsiienko, dev; +Cc: matan, rasland, stable

On 1/17/2020 2:59 PM, Viacheslav Ovsiienko wrote:
> The mlx5 datapath does not implement any endianness conversions
> for the metadata being sent and received to provide the better
> performance (because these conversions would be performed for
> each packet). These metadata are also involved into flow processing
> (there might be some flows matching on metadata patterns or setting
> the new metadata values) inside the NIC. It order to configure
> hardware in correct way all necessary endianness conversions are
> done by rte_flow handling code (only once on flow creation). This
> patch fixes one of these conversions for the little-endian hosts
> in case if META/MARK items are less than 32 bits.
> 
> Fixes: acfcd5c52f94 ("net/mlx5: update meta register matcher set")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
> Acked-by: Matan Azrad <matan@mellanox.com>
> ---
> v1: - http://patchwork.dpdk.org/patch/64125/
> v2: - commit message is rewritten
> 

Applied to dpdk-next-net/master, thanks.

^ permalink raw reply	[flat|nested] 5+ messages in thread

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2019-12-24 14:20 [dpdk-stable] [PATCH] net/mlx5: fix metadata item endianness conversion Viacheslav Ovsiienko
2020-01-06 14:44 ` Matan Azrad
2020-01-08  9:03 ` Raslan Darawsheh
2020-01-17 14:59 ` [dpdk-stable] [PATCH v2] " Viacheslav Ovsiienko
2020-01-17 17:19   ` Ferruh Yigit

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