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Wed, 6 Sep 2017 10:54:24 +0000 From: Shachar Beiser To: Adrien Mazarguil CC: "dev@dpdk.org" , =?iso-8859-1?Q?N=E9lio_Laranjeiro?= , "stable@dpdk.org" Thread-Topic: [PATCH v2 3/3] net/mlx5: fix interrupt enable return value Thread-Index: AQHTJkelbfFbH378VESDU+c/ZxeGR6KmSNcAgAFmnSA= Date: Wed, 6 Sep 2017 10:54:24 +0000 Message-ID: References: <20170905132720.GD4301@6wind.com> In-Reply-To: <20170905132720.GD4301@6wind.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=shacharbe@mellanox.com; x-originating-ip: [193.47.165.251] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM2PR05MB1041; 6:Aru2QlszLsYRGdn/DS4rpdNwFE0j50iMy3uQ/mSA8BQrk+qmEMK6lVp59NPKyyMh1TWxCY7l8ssPDIhW6fxStMQ8hSbVZUHMt32wf9OuSVPLMDqExOq1FjkxjrYBnmlR5AnQKkbce1HOVthPhpoFe9MGZ+4FxLu0kAyFFv8JzkahzJ4hLRM0p4oEuaxNbcimpJ0KAOK65bHC8ISWg6q6RDEZeLwg4p8aH0dy22aDXx3CJw+gvkfcbZWgfNeqFrT8aBbCIXfR1eEjhCU1wqxR4S3Lu6ni+0SzpH6tcTg0RfZhNi6Ui3YvehiGnhmPIMEtRIJf1opUdKsIQQGfbIyRkg==; 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DIR:OUT; SFP:1101; SCL:1; SRVR:AM2PR05MB1041; H:AM2PR05MB0689.eurprd05.prod.outlook.com; FPR:; SPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Sep 2017 10:54:24.2931 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM2PR05MB1041 Subject: Re: [dpdk-stable] [PATCH v2 3/3] net/mlx5: fix interrupt enable return value X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Sep 2017 10:54:27 -0000 Hi , The problem was that the value ret was not set to 0. As a result we got a warning message: WARN("unable to arm interrupt on rx queue %d", rx_queue_id); The fix is ret =3D0; I was looking with Nelio for the right commits that this bug fixes = I am=20 pretty sure that this ret value was not initialized. -Shachar Beiser. > -----Original Message----- > From: Adrien Mazarguil [mailto:adrien.mazarguil@6wind.com] > Sent: Tuesday, September 5, 2017 4:27 PM > To: Shachar Beiser > Cc: dev@dpdk.org; N=E9lio Laranjeiro ; > stable@dpdk.org > Subject: Re: [PATCH v2 3/3] net/mlx5: fix interrupt enable return value >=20 > Hi Shachar, >=20 > On Tue, Sep 05, 2017 at 01:04:38PM +0000, Shachar Beiser wrote: > > return value is sometimes returned uninitialized > > > > Fixes: e1016cb73383 ("net/mlx5: fix Rx interrupts management") > > Fixes: b18042fb8f49 ("net/mlx5: fix misplaced Rx interrupts > > functions") > > > > Cc: adrien.mazarguil@6wind.com > > Cc: stable@dpdk.org > > > > Signed-off-by: Shachar Beiser >=20 > Looks like in both commits, ret is properly initialized so I'm wondering = if the > fixes line is right? Did you even get a compilation error? >=20 > Otherwise, you should drop this patch from the series. >=20 > > --- > > drivers/net/mlx5/mlx5_rxq.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c > > index 437dc02..24887fb 100644 > > --- a/drivers/net/mlx5/mlx5_rxq.c > > +++ b/drivers/net/mlx5/mlx5_rxq.c > > @@ -1330,7 +1330,7 @@ > > struct priv *priv =3D mlx5_get_priv(dev); > > struct rxq *rxq =3D (*priv->rxqs)[rx_queue_id]; > > struct rxq_ctrl *rxq_ctrl =3D container_of(rxq, struct rxq_ctrl, rxq)= ; > > - int ret; > > + int ret =3D 0; > > > > if (!rxq || !rxq_ctrl->channel) { > > ret =3D EINVAL; > > -- > > 1.8.3.1 > > >=20 > -- > Adrien Mazarguil > 6WIND