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DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Feb 2022 08:29:59.5387 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f51246e3-9008-4d80-b5e0-08d9ec6f86ba X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT033.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR0802MB2147 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org > -----Original Message----- > From: Slava Ovsiienko > Sent: Thursday, February 10, 2022 4:17 PM > To: Ruifeng Wang ; Matan Azrad > > Cc: dev@dpdk.org; Honnappa Nagarahalli > ; stable@dpdk.org; nd ; > nd > Subject: RE: [PATCH] net/mlx5: fix risk in Rx descriptor read in NEON vec= tor > path >=20 > Hi Ruifeng, Hi Slava, >=20 > Patch looks reasonable, thank you. > Just curious - did you see the real issue with re-ordering in this code > fragment? No real issue was seen. It is analysis from architecture perspective. > And, please, let us do performance check. Sure. Thank you. >=20 > With best regards, > Slava >=20 > > -----Original Message----- > > From: Ruifeng Wang > > Sent: Thursday, February 10, 2022 8:25 > > To: Matan Azrad ; Slava Ovsiienko > > > > Cc: dev@dpdk.org; Honnappa Nagarahalli > ; > > stable@dpdk.org; nd ; Ruifeng Wang > ; > > nd > > Subject: RE: [PATCH] net/mlx5: fix risk in Rx descriptor read in NEON > > vector path > > > > Ping. > > Please could you help to review this patch? > > > > Thanks. > > Ruifeng > > > > > -----Original Message----- > > > From: Ruifeng Wang > > > Sent: Tuesday, January 4, 2022 11:01 AM > > > To: matan@nvidia.com; viacheslavo@nvidia.com > > > Cc: dev@dpdk.org; Honnappa Nagarahalli > > ; > > > stable@dpdk.org; nd ; Ruifeng Wang > > > > > Subject: [PATCH] net/mlx5: fix risk in Rx descriptor read in NEON > > > vector path > > > > > > In NEON vector PMD, vector load loads two contiguous 8B of > > > descriptor data into vector register. Given vector load ensures no > > > 16B atomicity, read of the word that includes op_own field could be > > > reordered after read of other words. In this case, some words could > contain invalid data. > > > > > > Reloaded qword0 after read barrier to update vector register. This > > > ensures that the fetched data is correct. > > > > > > Testpmd single core test on N1SDP/ThunderX2 showed no performance > > > drop. > > > > > > Fixes: 1742c2d9fab0 ("net/mlx5: fix synchronization on polling Rx > > > completions") > > > Cc: stable@dpdk.org > > > > > > Signed-off-by: Ruifeng Wang > > > --- > > > drivers/net/mlx5/mlx5_rxtx_vec_neon.h | 8 ++++++++ > > > 1 file changed, 8 insertions(+) > > > > > > diff --git a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h > > > b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h > > > index b1d16baa61..b1ec615b51 100644 > > > --- a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h > > > +++ b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h > > > @@ -647,6 +647,14 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, > > > volatile struct mlx5_cqe *cq, > > > c0 =3D vld1q_u64((uint64_t *)(p0 + 48)); > > > /* Synchronize for loading the rest of blocks. */ > > > rte_io_rmb(); > > > + /* B.0 (CQE 3) reload lower half of the block. */ > > > + c3 =3D vld1q_lane_u64((uint64_t *)(p3 + 48), c3, 0); > > > + /* B.0 (CQE 2) reload lower half of the block. */ > > > + c2 =3D vld1q_lane_u64((uint64_t *)(p2 + 48), c2, 0); > > > + /* B.0 (CQE 1) reload lower half of the block. */ > > > + c1 =3D vld1q_lane_u64((uint64_t *)(p1 + 48), c1, 0); > > > + /* B.0 (CQE 0) reload lower half of the block. */ > > > + c0 =3D vld1q_lane_u64((uint64_t *)(p0 + 48), c0, 0); > > > /* Prefetch next 4 CQEs. */ > > > if (pkts_n - pos >=3D 2 * MLX5_VPMD_DESCS_PER_LOOP) { > > > unsigned int next =3D pos + > > > MLX5_VPMD_DESCS_PER_LOOP; > > > -- > > > 2.25.1