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CAT:NONE; SFS:(13230028)(4636009)(396003)(376002)(39860400002)(136003)(346002)(451199021)(36840700001)(40470700004)(46966006)(4326008)(316002)(450100002)(70206006)(41300700001)(70586007)(186003)(54906003)(2906002)(110136005)(478600001)(8936002)(8676002)(5660300002)(52536014)(40460700003)(36860700001)(7696005)(9686003)(53546011)(33656002)(81166007)(82740400003)(356005)(6506007)(40480700001)(26005)(55016003)(336012)(83380400001)(47076005)(86362001)(82310400005)(23180200003); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jun 2023 10:20:28.5333 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0e049e4b-5691-415b-ec38-08db6bf7cf8c X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT032.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR08MB5886 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org > -----Original Message----- > From: Min Zhou > Sent: Tuesday, June 13, 2023 5:44 PM > To: thomas@monjalon.net; qi.z.zhang@intel.com; mb@smartsharesystems.com; > konstantin.v.ananyev@yandex.ru; Ruifeng Wang ; > drc@linux.vnet.ibm.com; roretzla@linux.microsoft.com; qiming.yang@intel.c= om; > wenjun1.wu@intel.com; zhoumin@loongson.cn > Cc: dev@dpdk.org; stable@dpdk.org; maobibo@loongson.cn; jiawenwu@trustnet= ic.com > Subject: [PATCH v4] net/ixgbe: add proper memory barriers for some Rx fun= ctions >=20 > Segmentation fault has been observed while running the > ixgbe_recv_pkts_lro() function to receive packets on the Loongson 3C5000 = processor which > has 64 cores and 4 NUMA nodes. >=20 > From the ixgbe_recv_pkts_lro() function, we found that as long as the fir= st packet has the > EOP bit set, and the length of this packet is less than or equal to rxq->= crc_len, the > segmentation fault will definitely happen even though on the other platfo= rms. For example, > if we made the first packet which had the EOP bit set had a zero length b= y force, the > segmentation fault would happen on X86. >=20 > Because when processd the first packet the first_seg->next will be NULL, = if at the same > time this packet has the EOP bit set and its length is less than or equal= to rxq->crc_len, > the following loop will be executed: >=20 > for (lp =3D first_seg; lp->next !=3D rxm; lp =3D lp->next) > ; >=20 > We know that the first_seg->next will be NULL under this condition. So th= e expression of > lp->next->next will cause the segmentation fault. >=20 > Normally, the length of the first packet with EOP bit set will be greater= than rxq- > >crc_len. However, the out-of-order execution of CPU may make the read or= dering of the > status and the rest of the descriptor fields in this function not be corr= ect. The related > codes are as following: >=20 > rxdp =3D &rx_ring[rx_id]; > #1 staterr =3D rte_le_to_cpu_32(rxdp->wb.upper.status_error); >=20 > if (!(staterr & IXGBE_RXDADV_STAT_DD)) > break; >=20 > #2 rxd =3D *rxdp; >=20 > The sentence #2 may be executed before sentence #1. This action is likely= to make the > ready packet zero length. If the packet is the first packet and has the E= OP bit set, the > above segmentation fault will happen. >=20 > So, we should add a proper memory barrier to ensure the read ordering be = correct. We also > did the same thing in the ixgbe_recv_pkts() function to make the rxd data= be valid even > though we did not find segmentation fault in this function. >=20 > Fixes: 8eecb3295ae ("ixgbe: add LRO support") > Cc: stable@dpdk.org >=20 > Signed-off-by: Min Zhou > --- > v4: > - Replace rte_smp_rmb() with rte_atomic_thread_fence() as the proper memo= ry > barrier > --- > v3: > - Use rte_smp_rmb() as the proper memory barrier instead of rte_rmb() > --- > v2: > - Make the calling of rte_rmb() for all platforms > --- >=20 > drivers/net/ixgbe/ixgbe_rxtx.c | 47 +++++++++++++++------------------- > 1 file changed, 21 insertions(+), 26 deletions(-) >=20 > diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxt= x.c index > 6cbb992823..61f17cd90b 100644 > --- a/drivers/net/ixgbe/ixgbe_rxtx.c > +++ b/drivers/net/ixgbe/ixgbe_rxtx.c > @@ -1817,11 +1817,22 @@ ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf *= *rx_pkts, > * of accesses cannot be reordered by the compiler. If they were > * not volatile, they could be reordered which could lead to > * using invalid descriptor fields when read from rxd. > + * > + * Meanwhile, to prevent the CPU from executing out of order, we > + * need to use a proper memory barrier to ensure the memory > + * ordering below. > */ > rxdp =3D &rx_ring[rx_id]; > staterr =3D rxdp->wb.upper.status_error; > if (!(staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD))) > break; > + > + /* > + * Use acquire fence to ensure that status_error which includes > + * DD bit is loaded before loading of other descriptor words. > + */ > + rte_atomic_thread_fence(__ATOMIC_ACQUIRE); > + > rxd =3D *rxdp; >=20 > /* > @@ -2088,32 +2099,10 @@ ixgbe_recv_pkts_lro(void *rx_queue, struct rte_mb= uf **rx_pkts, > uint16_t nb_pkts, >=20 > next_desc: > /* > - * The code in this whole file uses the volatile pointer to > - * ensure the read ordering of the status and the rest of the > - * descriptor fields (on the compiler level only!!!). This is so > - * UGLY - why not to just use the compiler barrier instead? DPDK > - * even has the rte_compiler_barrier() for that. > - * > - * But most importantly this is just wrong because this doesn't > - * ensure memory ordering in a general case at all. For > - * instance, DPDK is supposed to work on Power CPUs where > - * compiler barrier may just not be enough! > - * > - * I tried to write only this function properly to have a > - * starting point (as a part of an LRO/RSC series) but the > - * compiler cursed at me when I tried to cast away the > - * "volatile" from rx_ring (yes, it's volatile too!!!). So, I'm > - * keeping it the way it is for now. > - * > - * The code in this file is broken in so many other places and > - * will just not work on a big endian CPU anyway therefore the > - * lines below will have to be revisited together with the rest > - * of the ixgbe PMD. > - * > - * TODO: > - * - Get rid of "volatile" and let the compiler do its job. > - * - Use the proper memory barrier (rte_rmb()) to ensure the > - * memory ordering below. > + * "Volatile" only prevents caching of the variable marked > + * volatile. Most important, "volatile" cannot prevent the CPU > + * from executing out of order. So, it is necessary to use a > + * proper memory barrier to ensure the memory ordering below. > */ > rxdp =3D &rx_ring[rx_id]; > staterr =3D rte_le_to_cpu_32(rxdp->wb.upper.status_error); > @@ -2121,6 +2110,12 @@ ixgbe_recv_pkts_lro(void *rx_queue, struct rte_mbu= f **rx_pkts, > uint16_t nb_pkts, > if (!(staterr & IXGBE_RXDADV_STAT_DD)) > break; >=20 > + /* > + * Use acquire fence to ensure that status_error which includes > + * DD bit is loaded before loading of other descriptor words. > + */ > + rte_atomic_thread_fence(__ATOMIC_ACQUIRE); > + > rxd =3D *rxdp; >=20 > PMD_RX_LOG(DEBUG, "port_id=3D%u queue_id=3D%u rx_id=3D%u " > -- > 2.31.1 Reviewed-by: Ruifeng Wang