From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C3C47A0C4C for ; Wed, 1 Dec 2021 11:32:01 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BE4F040140; Wed, 1 Dec 2021 11:32:01 +0100 (CET) Received: from smtp-relay-internal-1.canonical.com (smtp-relay-internal-1.canonical.com [185.125.188.123]) by mails.dpdk.org (Postfix) with ESMTP id 5086740140 for ; Wed, 1 Dec 2021 11:32:00 +0100 (CET) Received: from mail-qk1-f200.google.com (mail-qk1-f200.google.com [209.85.222.200]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-internal-1.canonical.com (Postfix) with ESMTPS id 002EB3F1B2 for ; Wed, 1 Dec 2021 10:31:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical.com; s=20210705; t=1638354720; bh=CsupM1Kzm0xfvJwqbAle4rfH+r0Y/+NaAc9Xvq0LNqg=; h=MIME-Version:References:In-Reply-To:From:Date:Message-ID:Subject: To:Cc:Content-Type; b=Zns1MLerKUVH/N6eyhOt2uC4BNkkwYHZm8OUisiPjzHldqdOEd8x9twCEx6koSnjt hc/1Q36E8LofYkWHILSmmT67p+5hvFmZE0WVTMgK3Wz/tI0czCWswIP+tKVLSkYS8l eQrcbJ17b5urupG6So+EcKMI8p+qGVvskNBR4K9Z619D/VD+Sf1W8nVKHZfTFjiuk4 OiGVIBAMxGl09OTkA2C2pdwK32Ep4hf4VeKN5lWB99jQqDEnw3DeW4uAes9o1ZYLbh EiPb7saIDCHexkS0BLt6P4xgw8QNBadqJb4O/fgVPJPs0KUsbfW8G/WcrjACHXIZEP gZajzvZlZtcdA== Received: by mail-qk1-f200.google.com with SMTP id h8-20020a05620a284800b0045ec745583cso32478459qkp.6 for ; Wed, 01 Dec 2021 02:31:59 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=CsupM1Kzm0xfvJwqbAle4rfH+r0Y/+NaAc9Xvq0LNqg=; b=JRoUb90cPa8PAjX/qw8VUemm9AZ6AbpvoxuCJzUlirg9elR+3tXAknOFc0aZ4DxwlO vLIayBD057Gwl4i3eTl3I7DTBG/pTWKJ/+RwD2HRRK+s73b9jZ6iTTLPy9lTayxuzQ2u APYxBfoe5kN4GJ3MqdU3m4raue4e8hLUHCfPD0Lw8VUMnBfx/0qm+eCWuzM+g4vhyfVr 7ei/W0k4JlYJIKP8eb1a0cq1a04org/4jnpCcvxqifACYT3qEIMLDrYnfLI/mBhB9ON2 UvpSC1jTKd1fq/X/Vt8XsT3LVDPXQ3+Fhacb45qxEB9SrXkIKfBnxxCC5sxZYo278XnI STkw== X-Gm-Message-State: AOAM530H/dwFxpKOjrJZ6YboKZpvsg+mbopBXaKGroG0gmbgzzwDFcxR AMA5Hlf+6+tBPeE7MMeODJ603NlLbIfLwTcPPoHW/t+u1eST0juKzuOsp0u7qY4TF/5nt+iG4L7 Gac/OIE7QafUnV2nWr7bw3UZodnjE/9K6uSCaSjU/ X-Received: by 2002:a05:620a:172c:: with SMTP id az44mr5022781qkb.93.1638354719114; Wed, 01 Dec 2021 02:31:59 -0800 (PST) X-Google-Smtp-Source: ABdhPJxENtAUtD/67nZ3UNkunqI5BbA7ppBFmO2C22fIgS0k9tzDBvUz7T4djyeJcS7UvUpgSyLutzJgFzLub2CEc1s= X-Received: by 2002:a05:620a:172c:: with SMTP id az44mr5022765qkb.93.1638354718950; Wed, 01 Dec 2021 02:31:58 -0800 (PST) MIME-Version: 1.0 References: <20211201065603.1559660-1-ruifeng.wang@arm.com> In-Reply-To: <20211201065603.1559660-1-ruifeng.wang@arm.com> From: Christian Ehrhardt Date: Wed, 1 Dec 2021 11:31:33 +0100 Message-ID: Subject: Re: [PATCH 19.11] net/i40e: fix risk in descriptor read in scalar Rx To: Ruifeng Wang Cc: stable@dpdk.org, nd@arm.com, Honnappa Nagarahalli Content-Type: text/plain; charset="UTF-8" X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org On Wed, Dec 1, 2021 at 7:56 AM Ruifeng Wang wrote: > > [ upstream commit c4d3e8fbe485f244391797f7610512de377675e0 ] > Thanks, applied > Rx descriptor is 16B/32B in size. If the DD bit is set, it indicates > that the rest of the descriptor words have valid values. Hence, the > word containing DD bit must be read first before reading the rest of > the descriptor words. > > Since the entire descriptor is not read atomically, on relaxed memory > ordered systems like Aarch64, read of the word containing DD field > could be reordered after read of other words. > > Read barrier is inserted between read of the word with DD field > and read of other words. The barrier ensures that the fetched data > is correct. > > Testpmd single core test showed no performance drop on x86 or N1SDP. > On ThunderX2, 22% performance regression was observed. > > Fixes: 7b0cf70135d1 ("net/i40e: support ARM platform") > > Signed-off-by: Ruifeng Wang > Reviewed-by: Honnappa Nagarahalli > --- > drivers/net/i40e/i40e_rxtx.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c > index 0d5c721b5..1fddd66b9 100644 > --- a/drivers/net/i40e/i40e_rxtx.c > +++ b/drivers/net/i40e/i40e_rxtx.c > @@ -702,6 +702,12 @@ i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) > break; > } > > + /** > + * Use acquire fence to ensure that qword1 which includes DD > + * bit is loaded before loading of other descriptor words. > + */ > + __atomic_thread_fence(__ATOMIC_ACQUIRE); > + > rxd = *rxdp; > nb_hold++; > rxe = &sw_ring[rx_id]; > @@ -818,6 +824,12 @@ i40e_recv_scattered_pkts(void *rx_queue, > break; > } > > + /** > + * Use acquire fence to ensure that qword1 which includes DD > + * bit is loaded before loading of other descriptor words. > + */ > + __atomic_thread_fence(__ATOMIC_ACQUIRE); > + > rxd = *rxdp; > nb_hold++; > rxe = &sw_ring[rx_id]; > -- > 2.25.1 > -- Christian Ehrhardt Staff Engineer, Ubuntu Server Canonical Ltd