From: Christian Ehrhardt <christian.ehrhardt@canonical.com>
To: Jiawei Wang <jiaweiw@nvidia.com>
Cc: viacheslavo@nvidia.com, orika@nvidia.com, rasland@nvidia.com,
Matan Azrad <matan@nvidia.com>,
Shahaf Shuler <shahafs@nvidia.com>, Ori Kam <orika@mellanox.com>,
Yongseok Koh <yskoh@mellanox.com>,
stable@dpdk.org
Subject: Re: [PATCH 19.11] net/mlx5: fix NIC egress flow mismatch in switchdev mode
Date: Mon, 14 Mar 2022 08:55:21 +0100 [thread overview]
Message-ID: <CAATJJ0K_PVTvrC4VppZ2K4Sf0+E74YbnxZV_W4pOPSa8s9m0og@mail.gmail.com> (raw)
In-Reply-To: <20220313083908.12990-1-jiaweiw@nvidia.com>
On Sun, Mar 13, 2022 at 9:39 AM Jiawei Wang <jiaweiw@nvidia.com> wrote:
>
> [ upstream commit 6d4f1066be6cd60a95f21ef07a16a3c3676c5cd9 ]
Thank you - applied to 19.11 stable
> When E-Switch mode was enabled, the NIC egress flows was implicitly
> appended with source vport to match on. If the metadata register C0
> was used to maintain the source vport, it was initialized to zero
> on packet steering engine entry, the flow could be hit only
> if source vport was zero, the register C0 of the packet was not correct
> to match in the TX side, this caused egress flow misses.
>
> This patch:
> - removes the implicit source vport match for NIC egress flow.
> - rejects the NIC egress flows on the representor ports at validation.
> - allows the internal NIC egress flows containing the TX_QUEUE items in
> order to not impact hairpins.
>
> Fixes: ce777b147bf8 ("net/mlx5: fix E-Switch flow without port item")
>
> Signed-off-by: Jiawei Wang <jiaweiw@nvidia.com>
> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
> Acked-by: Ori Kam <orika@nvidia.com>
> ---
> doc/guides/nics/mlx5.rst | 2 ++
> drivers/net/mlx5/mlx5_flow_dv.c | 26 +++++++++++++++++++++-----
> 2 files changed, 23 insertions(+), 5 deletions(-)
>
> diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
> index 546f0dd4c2..8f7b285271 100644
> --- a/doc/guides/nics/mlx5.rst
> +++ b/doc/guides/nics/mlx5.rst
> @@ -241,6 +241,8 @@ Limitations
> from the reference "Clock Queue" completions,
> the scheduled send timestamps should not be specified with non-zero MSB.
>
> +- The NIC egress flow rules on representor port are not supported.
> +
> Statistics
> ----------
>
> diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
> index dd62bbbbfb..f7e3d92045 100644
> --- a/drivers/net/mlx5/mlx5_flow_dv.c
> +++ b/drivers/net/mlx5/mlx5_flow_dv.c
> @@ -4833,8 +4833,10 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
> return ret;
> last_item = MLX5_FLOW_ITEM_TAG;
> break;
> - case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
> case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
> + last_item = MLX5_FLOW_ITEM_TX_QUEUE;
> + break;
> + case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
> break;
> default:
> return rte_flow_error_set(error, ENOTSUP,
> @@ -5313,6 +5315,18 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
> NULL, "too many header modify"
> " actions to support");
> }
> + /*
> + * Validation the NIC Egress flow on representor, except implicit
> + * hairpin default egress flow with TX_QUEUE item, other flows not
> + * work due to metadata regC0 mismatch.
> + */
> + if ((!attr->transfer && attr->egress) && priv->representor &&
> + !(item_flags & MLX5_FLOW_ITEM_TX_QUEUE))
> + return rte_flow_error_set(error, EINVAL,
> + RTE_FLOW_ERROR_TYPE_ITEM,
> + NULL,
> + "NIC egress rules on representors"
> + " is not supported");
> return 0;
> }
>
> @@ -7891,12 +7905,14 @@ __flow_dv_translate(struct rte_eth_dev *dev,
> /*
> * When E-Switch mode is enabled, we have two cases where we need to
> * set the source port manually.
> - * The first one, is in case of Nic steering rule, and the second is
> - * E-Switch rule where no port_id item was found. In both cases
> - * the source port is set according the current port in use.
> + * The first one, is in case of NIC ingress steering rule, and the
> + * second is E-Switch rule where no port_id item was found.
> + * In both cases the source port is set according the current port
> + * in use.
> */
> if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
> - (priv->representor || priv->master)) {
> + (priv->representor || priv->master) &&
> + !(attr->egress && !attr->transfer)) {
> if (flow_dv_translate_item_port_id(dev, match_mask,
> match_value, NULL))
> return -rte_errno;
> --
> 2.18.1
>
--
Christian Ehrhardt
Staff Engineer, Ubuntu Server
Canonical Ltd
prev parent reply other threads:[~2022-03-14 7:55 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-13 8:39 Jiawei Wang
2022-03-14 7:55 ` Christian Ehrhardt [this message]
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