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* [dpdk-stable] [PATCH] eal/x86: fix some CPU extended features
@ 2021-10-06 19:20 David Marchand
  2021-10-08 10:15 ` Bruce Richardson
  2021-10-08 12:07 ` [dpdk-stable] [PATCH v2 1/2] eal/x86: fix some CPU extended features definitions David Marchand
  0 siblings, 2 replies; 5+ messages in thread
From: David Marchand @ 2021-10-06 19:20 UTC (permalink / raw)
  To: dev; +Cc: stable, Bruce Richardson, Konstantin Ananyev

Caught while checking CPUID related stuff in OVS.

According to [1], for Structured Extended Feature Flags Enumeration Leaf
(EAX = 0x07H, ECX = 0):

- BMI1 is associated to EBX, bit 3 (was incorrectly 2),
- SMEP is associated to EBX, bit 7 (was incorrectly 6),
- BMI2 is associated to EBX, bit 8 (was incorrectly 7),
- ERMS is associated to EBX, bit 9 (was incorrectly 8),

This patch then sorts the rest of the extended features (leaf 0) for
readability.

1: https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

Fixes: af75078fece3 ("first public release")
Cc: stable@dpdk.org

Signed-off-by: David Marchand <david.marchand@redhat.com>
---
 lib/eal/x86/rte_cpuflags.c | 46 +++++++++++++++++++-------------------
 1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/lib/eal/x86/rte_cpuflags.c b/lib/eal/x86/rte_cpuflags.c
index d339734a8c..d6b518251b 100644
--- a/lib/eal/x86/rte_cpuflags.c
+++ b/lib/eal/x86/rte_cpuflags.c
@@ -100,18 +100,36 @@ const struct feature_entry rte_cpu_feature_table[] = {
 	FEAT_DEF(ENERGY_EFF, 0x00000006, 0, RTE_REG_ECX,  3)
 
 	FEAT_DEF(FSGSBASE, 0x00000007, 0, RTE_REG_EBX,  0)
-	FEAT_DEF(BMI1, 0x00000007, 0, RTE_REG_EBX,  2)
+	FEAT_DEF(BMI1, 0x00000007, 0, RTE_REG_EBX,  3)
 	FEAT_DEF(HLE, 0x00000007, 0, RTE_REG_EBX,  4)
 	FEAT_DEF(AVX2, 0x00000007, 0, RTE_REG_EBX,  5)
-	FEAT_DEF(SMEP, 0x00000007, 0, RTE_REG_EBX,  6)
-	FEAT_DEF(BMI2, 0x00000007, 0, RTE_REG_EBX,  7)
-	FEAT_DEF(ERMS, 0x00000007, 0, RTE_REG_EBX,  8)
+	FEAT_DEF(SMEP, 0x00000007, 0, RTE_REG_EBX,  7)
+	FEAT_DEF(BMI2, 0x00000007, 0, RTE_REG_EBX,  8)
+	FEAT_DEF(ERMS, 0x00000007, 0, RTE_REG_EBX,  9)
 	FEAT_DEF(INVPCID, 0x00000007, 0, RTE_REG_EBX, 10)
 	FEAT_DEF(RTM, 0x00000007, 0, RTE_REG_EBX, 11)
 	FEAT_DEF(AVX512F, 0x00000007, 0, RTE_REG_EBX, 16)
+	FEAT_DEF(AVX512DQ, 0x00000007, 0, RTE_REG_EBX, 17)
 	FEAT_DEF(RDSEED, 0x00000007, 0, RTE_REG_EBX, 18)
+	FEAT_DEF(AVX512IFMA, 0x00000007, 0, RTE_REG_EBX, 21)
+	FEAT_DEF(AVX512CD, 0x00000007, 0, RTE_REG_EBX, 28)
+	FEAT_DEF(AVX512BW, 0x00000007, 0, RTE_REG_EBX, 30)
+	FEAT_DEF(AVX512VL, 0x00000007, 0, RTE_REG_EBX, 31)
+
+	FEAT_DEF(AVX512VBMI, 0x00000007, 0, RTE_REG_ECX,  1)
+	FEAT_DEF(WAITPKG, 0x00000007, 0, RTE_REG_ECX,  5)
+	FEAT_DEF(AVX512VBMI2, 0x00000007, 0, RTE_REG_ECX,  6)
+	FEAT_DEF(GFNI, 0x00000007, 0, RTE_REG_ECX,  8)
+	FEAT_DEF(VAES, 0x00000007, 0, RTE_REG_ECX,  9)
+	FEAT_DEF(VPCLMULQDQ, 0x00000007, 0, RTE_REG_ECX, 10)
+	FEAT_DEF(AVX512VNNI, 0x00000007, 0, RTE_REG_ECX, 11)
+	FEAT_DEF(AVX512BITALG, 0x00000007, 0, RTE_REG_ECX, 12)
+	FEAT_DEF(AVX512VPOPCNTDQ, 0x00000007, 0, RTE_REG_ECX, 14)
+	FEAT_DEF(CLDEMOTE, 0x00000007, 0, RTE_REG_ECX, 25)
+	FEAT_DEF(MOVDIRI, 0x00000007, 0, RTE_REG_ECX, 27)
+	FEAT_DEF(MOVDIR64B, 0x00000007, 0, RTE_REG_ECX, 28)
 
-	FEAT_DEF(WAITPKG, 0x00000007, 0, RTE_REG_ECX, 5)
+	FEAT_DEF(AVX512VP2INTERSECT, 0x00000007, 0, RTE_REG_EDX,  8)
 
 	FEAT_DEF(LAHF_SAHF, 0x80000001, 0, RTE_REG_ECX,  0)
 	FEAT_DEF(LZCNT, 0x80000001, 0, RTE_REG_ECX,  4)
@@ -123,24 +141,6 @@ const struct feature_entry rte_cpu_feature_table[] = {
 	FEAT_DEF(EM64T, 0x80000001, 0, RTE_REG_EDX, 29)
 
 	FEAT_DEF(INVTSC, 0x80000007, 0, RTE_REG_EDX,  8)
-
-	FEAT_DEF(AVX512DQ, 0x00000007, 0, RTE_REG_EBX, 17)
-	FEAT_DEF(AVX512IFMA, 0x00000007, 0, RTE_REG_EBX, 21)
-	FEAT_DEF(AVX512CD, 0x00000007, 0, RTE_REG_EBX, 28)
-	FEAT_DEF(AVX512BW, 0x00000007, 0, RTE_REG_EBX, 30)
-	FEAT_DEF(AVX512VL, 0x00000007, 0, RTE_REG_EBX, 31)
-	FEAT_DEF(AVX512VBMI, 0x00000007, 0, RTE_REG_ECX, 1)
-	FEAT_DEF(AVX512VBMI2, 0x00000007, 0, RTE_REG_ECX, 6)
-	FEAT_DEF(GFNI, 0x00000007, 0, RTE_REG_ECX, 8)
-	FEAT_DEF(VAES, 0x00000007, 0, RTE_REG_ECX, 9)
-	FEAT_DEF(VPCLMULQDQ, 0x00000007, 0, RTE_REG_ECX, 10)
-	FEAT_DEF(AVX512VNNI, 0x00000007, 0, RTE_REG_ECX, 11)
-	FEAT_DEF(AVX512BITALG, 0x00000007, 0, RTE_REG_ECX, 12)
-	FEAT_DEF(AVX512VPOPCNTDQ, 0x00000007, 0, RTE_REG_ECX,  14)
-	FEAT_DEF(CLDEMOTE, 0x00000007, 0, RTE_REG_ECX, 25)
-	FEAT_DEF(MOVDIRI, 0x00000007, 0, RTE_REG_ECX, 27)
-	FEAT_DEF(MOVDIR64B, 0x00000007, 0, RTE_REG_ECX, 28)
-	FEAT_DEF(AVX512VP2INTERSECT, 0x00000007, 0, RTE_REG_EDX, 8)
 };
 
 int
-- 
2.23.0


^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [dpdk-stable] [PATCH] eal/x86: fix some CPU extended features
  2021-10-06 19:20 [dpdk-stable] [PATCH] eal/x86: fix some CPU extended features David Marchand
@ 2021-10-08 10:15 ` Bruce Richardson
  2021-10-08 11:08   ` David Marchand
  2021-10-08 12:07 ` [dpdk-stable] [PATCH v2 1/2] eal/x86: fix some CPU extended features definitions David Marchand
  1 sibling, 1 reply; 5+ messages in thread
From: Bruce Richardson @ 2021-10-08 10:15 UTC (permalink / raw)
  To: David Marchand; +Cc: dev, stable, Konstantin Ananyev

On Wed, Oct 06, 2021 at 09:20:08PM +0200, David Marchand wrote:
> Caught while checking CPUID related stuff in OVS.
> 
> According to [1], for Structured Extended Feature Flags Enumeration Leaf
> (EAX = 0x07H, ECX = 0):
> 
> - BMI1 is associated to EBX, bit 3 (was incorrectly 2),
> - SMEP is associated to EBX, bit 7 (was incorrectly 6),
> - BMI2 is associated to EBX, bit 8 (was incorrectly 7),
> - ERMS is associated to EBX, bit 9 (was incorrectly 8),
> 
> This patch then sorts the rest of the extended features (leaf 0) for
> readability.
> 
> 1: https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
> 
> Fixes: af75078fece3 ("first public release")

Wow, I'm surprised at it being incorrect this long, but checking the
original commit of code, it does indeed seem true that this is the correct
fixes line!

> Cc: stable@dpdk.org
> 
> Signed-off-by: David Marchand <david.marchand@redhat.com>

Acked-by: Bruce Richardson <bruce.richardson@intel.com>

Ideally, I think the fixes should go in a separate patch from the
reordering, but I don't feel strongly about it so this is ok as either one
or two patches IMHO.

> ---
>  lib/eal/x86/rte_cpuflags.c | 46 +++++++++++++++++++-------------------
>  1 file changed, 23 insertions(+), 23 deletions(-)
> 
> diff --git a/lib/eal/x86/rte_cpuflags.c b/lib/eal/x86/rte_cpuflags.c
> index d339734a8c..d6b518251b 100644
> --- a/lib/eal/x86/rte_cpuflags.c
> +++ b/lib/eal/x86/rte_cpuflags.c
> @@ -100,18 +100,36 @@ const struct feature_entry rte_cpu_feature_table[] = {
>  	FEAT_DEF(ENERGY_EFF, 0x00000006, 0, RTE_REG_ECX,  3)
>  
>  	FEAT_DEF(FSGSBASE, 0x00000007, 0, RTE_REG_EBX,  0)
> -	FEAT_DEF(BMI1, 0x00000007, 0, RTE_REG_EBX,  2)
> +	FEAT_DEF(BMI1, 0x00000007, 0, RTE_REG_EBX,  3)
>  	FEAT_DEF(HLE, 0x00000007, 0, RTE_REG_EBX,  4)
>  	FEAT_DEF(AVX2, 0x00000007, 0, RTE_REG_EBX,  5)
> -	FEAT_DEF(SMEP, 0x00000007, 0, RTE_REG_EBX,  6)
> -	FEAT_DEF(BMI2, 0x00000007, 0, RTE_REG_EBX,  7)
> -	FEAT_DEF(ERMS, 0x00000007, 0, RTE_REG_EBX,  8)
> +	FEAT_DEF(SMEP, 0x00000007, 0, RTE_REG_EBX,  7)
> +	FEAT_DEF(BMI2, 0x00000007, 0, RTE_REG_EBX,  8)
> +	FEAT_DEF(ERMS, 0x00000007, 0, RTE_REG_EBX,  9)
>  	FEAT_DEF(INVPCID, 0x00000007, 0, RTE_REG_EBX, 10)
>  	FEAT_DEF(RTM, 0x00000007, 0, RTE_REG_EBX, 11)
>  	FEAT_DEF(AVX512F, 0x00000007, 0, RTE_REG_EBX, 16)
> +	FEAT_DEF(AVX512DQ, 0x00000007, 0, RTE_REG_EBX, 17)
>  	FEAT_DEF(RDSEED, 0x00000007, 0, RTE_REG_EBX, 18)
> +	FEAT_DEF(AVX512IFMA, 0x00000007, 0, RTE_REG_EBX, 21)
> +	FEAT_DEF(AVX512CD, 0x00000007, 0, RTE_REG_EBX, 28)
> +	FEAT_DEF(AVX512BW, 0x00000007, 0, RTE_REG_EBX, 30)
> +	FEAT_DEF(AVX512VL, 0x00000007, 0, RTE_REG_EBX, 31)
> +
> +	FEAT_DEF(AVX512VBMI, 0x00000007, 0, RTE_REG_ECX,  1)
> +	FEAT_DEF(WAITPKG, 0x00000007, 0, RTE_REG_ECX,  5)
> +	FEAT_DEF(AVX512VBMI2, 0x00000007, 0, RTE_REG_ECX,  6)
> +	FEAT_DEF(GFNI, 0x00000007, 0, RTE_REG_ECX,  8)
> +	FEAT_DEF(VAES, 0x00000007, 0, RTE_REG_ECX,  9)
> +	FEAT_DEF(VPCLMULQDQ, 0x00000007, 0, RTE_REG_ECX, 10)
> +	FEAT_DEF(AVX512VNNI, 0x00000007, 0, RTE_REG_ECX, 11)
> +	FEAT_DEF(AVX512BITALG, 0x00000007, 0, RTE_REG_ECX, 12)
> +	FEAT_DEF(AVX512VPOPCNTDQ, 0x00000007, 0, RTE_REG_ECX, 14)
> +	FEAT_DEF(CLDEMOTE, 0x00000007, 0, RTE_REG_ECX, 25)
> +	FEAT_DEF(MOVDIRI, 0x00000007, 0, RTE_REG_ECX, 27)
> +	FEAT_DEF(MOVDIR64B, 0x00000007, 0, RTE_REG_ECX, 28)
>  
> -	FEAT_DEF(WAITPKG, 0x00000007, 0, RTE_REG_ECX, 5)
> +	FEAT_DEF(AVX512VP2INTERSECT, 0x00000007, 0, RTE_REG_EDX,  8)
>  
>  	FEAT_DEF(LAHF_SAHF, 0x80000001, 0, RTE_REG_ECX,  0)
>  	FEAT_DEF(LZCNT, 0x80000001, 0, RTE_REG_ECX,  4)
> @@ -123,24 +141,6 @@ const struct feature_entry rte_cpu_feature_table[] = {
>  	FEAT_DEF(EM64T, 0x80000001, 0, RTE_REG_EDX, 29)
>  
>  	FEAT_DEF(INVTSC, 0x80000007, 0, RTE_REG_EDX,  8)
> -
> -	FEAT_DEF(AVX512DQ, 0x00000007, 0, RTE_REG_EBX, 17)
> -	FEAT_DEF(AVX512IFMA, 0x00000007, 0, RTE_REG_EBX, 21)
> -	FEAT_DEF(AVX512CD, 0x00000007, 0, RTE_REG_EBX, 28)
> -	FEAT_DEF(AVX512BW, 0x00000007, 0, RTE_REG_EBX, 30)
> -	FEAT_DEF(AVX512VL, 0x00000007, 0, RTE_REG_EBX, 31)
> -	FEAT_DEF(AVX512VBMI, 0x00000007, 0, RTE_REG_ECX, 1)
> -	FEAT_DEF(AVX512VBMI2, 0x00000007, 0, RTE_REG_ECX, 6)
> -	FEAT_DEF(GFNI, 0x00000007, 0, RTE_REG_ECX, 8)
> -	FEAT_DEF(VAES, 0x00000007, 0, RTE_REG_ECX, 9)
> -	FEAT_DEF(VPCLMULQDQ, 0x00000007, 0, RTE_REG_ECX, 10)
> -	FEAT_DEF(AVX512VNNI, 0x00000007, 0, RTE_REG_ECX, 11)
> -	FEAT_DEF(AVX512BITALG, 0x00000007, 0, RTE_REG_ECX, 12)
> -	FEAT_DEF(AVX512VPOPCNTDQ, 0x00000007, 0, RTE_REG_ECX,  14)
> -	FEAT_DEF(CLDEMOTE, 0x00000007, 0, RTE_REG_ECX, 25)
> -	FEAT_DEF(MOVDIRI, 0x00000007, 0, RTE_REG_ECX, 27)
> -	FEAT_DEF(MOVDIR64B, 0x00000007, 0, RTE_REG_ECX, 28)
> -	FEAT_DEF(AVX512VP2INTERSECT, 0x00000007, 0, RTE_REG_EDX, 8)
>  };
>  
>  int
> -- 
> 2.23.0
> 

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [dpdk-stable] [PATCH] eal/x86: fix some CPU extended features
  2021-10-08 10:15 ` Bruce Richardson
@ 2021-10-08 11:08   ` David Marchand
  0 siblings, 0 replies; 5+ messages in thread
From: David Marchand @ 2021-10-08 11:08 UTC (permalink / raw)
  To: Bruce Richardson; +Cc: dev, dpdk stable, Konstantin Ananyev

On Fri, Oct 8, 2021 at 12:15 PM Bruce Richardson
<bruce.richardson@intel.com> wrote:
>
> On Wed, Oct 06, 2021 at 09:20:08PM +0200, David Marchand wrote:
> > Caught while checking CPUID related stuff in OVS.
> >
> > According to [1], for Structured Extended Feature Flags Enumeration Leaf
> > (EAX = 0x07H, ECX = 0):
> >
> > - BMI1 is associated to EBX, bit 3 (was incorrectly 2),
> > - SMEP is associated to EBX, bit 7 (was incorrectly 6),
> > - BMI2 is associated to EBX, bit 8 (was incorrectly 7),
> > - ERMS is associated to EBX, bit 9 (was incorrectly 8),
> >
> > This patch then sorts the rest of the extended features (leaf 0) for
> > readability.
> >
> > 1: https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
> >
> > Fixes: af75078fece3 ("first public release")
>
> Wow, I'm surprised at it being incorrect this long, but checking the
> original commit of code, it does indeed seem true that this is the correct
> fixes line!
>
> > Cc: stable@dpdk.org
> >
> > Signed-off-by: David Marchand <david.marchand@redhat.com>
>
> Acked-by: Bruce Richardson <bruce.richardson@intel.com>
>
> Ideally, I think the fixes should go in a separate patch from the
> reordering, but I don't feel strongly about it so this is ok as either one
> or two patches IMHO.

I was reading the datasheet and comparing the defines one by one, so
easier with sorted defines.
Now that I identified the wrong entries, I am fine with splitting
since it eases backport on 19.11.

I'll send v2 with your ack on both.


-- 
David Marchand


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [dpdk-stable] [PATCH v2 1/2] eal/x86: fix some CPU extended features definitions
  2021-10-06 19:20 [dpdk-stable] [PATCH] eal/x86: fix some CPU extended features David Marchand
  2021-10-08 10:15 ` Bruce Richardson
@ 2021-10-08 12:07 ` David Marchand
  2021-10-12 19:06   ` David Marchand
  1 sibling, 1 reply; 5+ messages in thread
From: David Marchand @ 2021-10-08 12:07 UTC (permalink / raw)
  To: dev; +Cc: stable, Bruce Richardson, Konstantin Ananyev

Caught while checking CPUID related stuff in OVS.

According to [1], for Structured Extended Feature Flags Enumeration Leaf
(EAX = 0x07H, ECX = 0):

- BMI1 is associated to EBX, bit 3 (was incorrectly 2),
- SMEP is associated to EBX, bit 7 (was incorrectly 6),
- BMI2 is associated to EBX, bit 8 (was incorrectly 7),
- ERMS is associated to EBX, bit 9 (was incorrectly 8),

1: https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

Fixes: af75078fece3 ("first public release")
Cc: stable@dpdk.org

Signed-off-by: David Marchand <david.marchand@redhat.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
---
 lib/eal/x86/rte_cpuflags.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/lib/eal/x86/rte_cpuflags.c b/lib/eal/x86/rte_cpuflags.c
index d339734a8c..378fc95396 100644
--- a/lib/eal/x86/rte_cpuflags.c
+++ b/lib/eal/x86/rte_cpuflags.c
@@ -100,12 +100,12 @@ const struct feature_entry rte_cpu_feature_table[] = {
 	FEAT_DEF(ENERGY_EFF, 0x00000006, 0, RTE_REG_ECX,  3)
 
 	FEAT_DEF(FSGSBASE, 0x00000007, 0, RTE_REG_EBX,  0)
-	FEAT_DEF(BMI1, 0x00000007, 0, RTE_REG_EBX,  2)
+	FEAT_DEF(BMI1, 0x00000007, 0, RTE_REG_EBX,  3)
 	FEAT_DEF(HLE, 0x00000007, 0, RTE_REG_EBX,  4)
 	FEAT_DEF(AVX2, 0x00000007, 0, RTE_REG_EBX,  5)
-	FEAT_DEF(SMEP, 0x00000007, 0, RTE_REG_EBX,  6)
-	FEAT_DEF(BMI2, 0x00000007, 0, RTE_REG_EBX,  7)
-	FEAT_DEF(ERMS, 0x00000007, 0, RTE_REG_EBX,  8)
+	FEAT_DEF(SMEP, 0x00000007, 0, RTE_REG_EBX,  7)
+	FEAT_DEF(BMI2, 0x00000007, 0, RTE_REG_EBX,  8)
+	FEAT_DEF(ERMS, 0x00000007, 0, RTE_REG_EBX,  9)
 	FEAT_DEF(INVPCID, 0x00000007, 0, RTE_REG_EBX, 10)
 	FEAT_DEF(RTM, 0x00000007, 0, RTE_REG_EBX, 11)
 	FEAT_DEF(AVX512F, 0x00000007, 0, RTE_REG_EBX, 16)
-- 
2.23.0


^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [dpdk-stable] [PATCH v2 1/2] eal/x86: fix some CPU extended features definitions
  2021-10-08 12:07 ` [dpdk-stable] [PATCH v2 1/2] eal/x86: fix some CPU extended features definitions David Marchand
@ 2021-10-12 19:06   ` David Marchand
  0 siblings, 0 replies; 5+ messages in thread
From: David Marchand @ 2021-10-12 19:06 UTC (permalink / raw)
  To: dev; +Cc: dpdk stable, Bruce Richardson, Konstantin Ananyev

On Fri, Oct 8, 2021 at 2:07 PM David Marchand <david.marchand@redhat.com> wrote:
>
> Caught while checking CPUID related stuff in OVS.
>
> According to [1], for Structured Extended Feature Flags Enumeration Leaf
> (EAX = 0x07H, ECX = 0):
>
> - BMI1 is associated to EBX, bit 3 (was incorrectly 2),
> - SMEP is associated to EBX, bit 7 (was incorrectly 6),
> - BMI2 is associated to EBX, bit 8 (was incorrectly 7),
> - ERMS is associated to EBX, bit 9 (was incorrectly 8),
>
> 1: https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
>
> Fixes: af75078fece3 ("first public release")
> Cc: stable@dpdk.org
>
> Signed-off-by: David Marchand <david.marchand@redhat.com>
> Acked-by: Bruce Richardson <bruce.richardson@intel.com>

Series applied, thanks.


-- 
David Marchand


^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2021-10-12 19:06 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-06 19:20 [dpdk-stable] [PATCH] eal/x86: fix some CPU extended features David Marchand
2021-10-08 10:15 ` Bruce Richardson
2021-10-08 11:08   ` David Marchand
2021-10-08 12:07 ` [dpdk-stable] [PATCH v2 1/2] eal/x86: fix some CPU extended features definitions David Marchand
2021-10-12 19:06   ` David Marchand

patches for DPDK stable branches

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