From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 48A9EA00C4 for ; Fri, 13 May 2022 13:47:47 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 369244114F; Fri, 13 May 2022 13:47:47 +0200 (CEST) Received: from mail-io1-f42.google.com (mail-io1-f42.google.com [209.85.166.42]) by mails.dpdk.org (Postfix) with ESMTP id B464C40DDE; Fri, 13 May 2022 13:47:44 +0200 (CEST) Received: by mail-io1-f42.google.com with SMTP id f4so8389356iov.2; Fri, 13 May 2022 04:47:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=A0CP/ZfLQpfQjrr7MIOPoHmFce8VWh9y4WGS3fJGkOo=; b=pITIJO3VuSrMDByFzfOSgihZBuYZcM6L/Nh0UdS5W+b3q6K4tBDRMwRGpLBUJXScmI sF0ewSRmhn8eu3urebN4+RX0b/l33ASlQiWd9OSSZpqZeJxi4HePpcizy4fitfziDtG8 T0Bl71NmfQAQFLz46t3sHrSXAjcAdqLwsSZzInE7ZhZ/LBZJ2nThciO1qhmzXXlV7Cgz i12q8jEtfIekG2B+d8nl4LQPvP7dSQmdZWBwv40d0AAH2PQdbQD92tRNReORPSTVWMRV EmDA6Pm/oAST1fIDp9p0DjuoLHgxTIaBVVrI8JMcP5tEyQ8rQzwDlfle4+wcrJPOxK71 Ggww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=A0CP/ZfLQpfQjrr7MIOPoHmFce8VWh9y4WGS3fJGkOo=; b=171wRNiZvRpUGfJyP6mvNWMdDItmyNuvWh7yoeEWl02KLeXg0c+sZYFqLl5hG0LAAy 1a4fzjx14BZjTzkQZ0wE1DWKC+FBoD4/6vqnfzZG0g5O/3o2/CUjTHHvtfiE281AO9os kB+k6D8IxLpCERIotqPVuqZVzOuW90H6KaMnpiDUyQXRB8akjsjSrhSmlszhipG5UbPH P0PFG0CddT72acaj2sUV/rzXSw1PyBP4Nfm9WPSa346igUUe0yQ+5mt+Bf252ZPao3Uh PyOMmdocfZmUQ86QXHyZZzSREcEBLosybCkj8PpBXuFQaegtnudsOnp4skCvbfWxUP3B /zoQ== X-Gm-Message-State: AOAM532clFjOmb69DlzcqHn2XPW+n9lKbcWru1HtN+A1/EmiCHVEGzkr Wdt8g7mCuDcB1MAR5QNigpvdDAhRO/nAE7kV/+QDr6QqZMU= X-Google-Smtp-Source: ABdhPJzNAC2BFo5N7p4Lwo60/j2iXpJj/g2owvuzZvhtS7gcHf/KhOkLIBBDgZQKNMeC8zqZn95KkjqO/r+eQ7xpIps= X-Received: by 2002:a05:6602:2c8b:b0:65a:cbc1:3d56 with SMTP id i11-20020a0566022c8b00b0065acbc13d56mr2037290iow.121.1652442464031; Fri, 13 May 2022 04:47:44 -0700 (PDT) MIME-Version: 1.0 References: <20220325105939.1117634-1-vfialko@marvell.com> In-Reply-To: <20220325105939.1117634-1-vfialko@marvell.com> From: Jerin Jacob Date: Fri, 13 May 2022 17:17:17 +0530 Message-ID: Subject: Re: [PATCH] event/cnxk: fix base pointer for SSO head wait To: Volodymyr Fialko Cc: dpdk-dev , Ankur Dwivedi , Anoob Joseph , Tejasree Kondoj , Pavan Nikhilesh , Shijith Thotton , Jerin Jacob , dpdk stable Content-Type: text/plain; charset="UTF-8" X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org On Fri, Mar 25, 2022 at 4:30 PM Volodymyr Fialko wrote: > > Function roc_sso_hws_head_wait() expects a base as input pointer, and it > will itself get tag_op from the base. By passing tag_op instead of base > pointer to this function will add SSOW_LF_GWS_TAG register offset twice, > which will lead to accessing wrong register. > > Fixes: 1f5b3d55c041 ("event/cnxk: store and reuse workslot status") > > Cc: stable@dpdk.org > > Signed-off-by: Volodymyr Fialko Acked-by: Jerin Jacob Applied to dpdk-next-net-eventdev/for-main. Thanks > --- > drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 4 ++-- > drivers/crypto/cnxk/cn10k_cryptodev_ops.h | 2 +- > drivers/crypto/cnxk/cn9k_cryptodev_ops.c | 4 ++-- > drivers/crypto/cnxk/cn9k_cryptodev_ops.h | 2 +- > drivers/event/cnxk/cn10k_worker.c | 3 +-- > drivers/event/cnxk/cn9k_worker.c | 7 +++---- > 6 files changed, 10 insertions(+), 12 deletions(-) > > diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c > index d217bbf383..1b08c67fea 100644 > --- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c > +++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c > @@ -265,7 +265,7 @@ cn10k_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops) > } > > uint16_t > -cn10k_cpt_crypto_adapter_enqueue(uintptr_t tag_op, struct rte_crypto_op *op) > +cn10k_cpt_crypto_adapter_enqueue(uintptr_t base, struct rte_crypto_op *op) > { > union rte_event_crypto_metadata *ec_mdata; > struct cpt_inflight_req *infl_req; > @@ -328,7 +328,7 @@ cn10k_cpt_crypto_adapter_enqueue(uintptr_t tag_op, struct rte_crypto_op *op) > } > > if (!rsp_info->sched_type) > - roc_sso_hws_head_wait(tag_op); > + roc_sso_hws_head_wait(base); > > lmt_arg = ROC_CN10K_CPT_LMT_ARG | (uint64_t)lmt_id; > roc_lmt_submit_steorl(lmt_arg, qp->lmtline.io_addr); > diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.h b/drivers/crypto/cnxk/cn10k_cryptodev_ops.h > index d7e9f87396..1ad4c16873 100644 > --- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.h > +++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.h > @@ -13,7 +13,7 @@ extern struct rte_cryptodev_ops cn10k_cpt_ops; > void cn10k_cpt_set_enqdeq_fns(struct rte_cryptodev *dev); > > __rte_internal > -uint16_t cn10k_cpt_crypto_adapter_enqueue(uintptr_t tag_op, > +uint16_t cn10k_cpt_crypto_adapter_enqueue(uintptr_t base, > struct rte_crypto_op *op); > __rte_internal > uintptr_t cn10k_cpt_crypto_adapter_dequeue(uintptr_t get_work1); > diff --git a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c > index ddba9d5dd0..d3858149c7 100644 > --- a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c > +++ b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c > @@ -317,7 +317,7 @@ cn9k_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops) > } > > uint16_t > -cn9k_cpt_crypto_adapter_enqueue(uintptr_t tag_op, struct rte_crypto_op *op) > +cn9k_cpt_crypto_adapter_enqueue(uintptr_t base, struct rte_crypto_op *op) > { > union rte_event_crypto_metadata *ec_mdata; > struct cpt_inflight_req *infl_req; > @@ -374,7 +374,7 @@ cn9k_cpt_crypto_adapter_enqueue(uintptr_t tag_op, struct rte_crypto_op *op) > } > > if (!rsp_info->sched_type) > - roc_sso_hws_head_wait(tag_op); > + roc_sso_hws_head_wait(base); > > cn9k_cpt_inst_submit(&inst, qp->lmtline.lmt_base, qp->lmtline.io_addr); > > diff --git a/drivers/crypto/cnxk/cn9k_cryptodev_ops.h b/drivers/crypto/cnxk/cn9k_cryptodev_ops.h > index 309f507346..9f6dc24603 100644 > --- a/drivers/crypto/cnxk/cn9k_cryptodev_ops.h > +++ b/drivers/crypto/cnxk/cn9k_cryptodev_ops.h > @@ -12,7 +12,7 @@ extern struct rte_cryptodev_ops cn9k_cpt_ops; > void cn9k_cpt_set_enqdeq_fns(struct rte_cryptodev *dev); > > __rte_internal > -uint16_t cn9k_cpt_crypto_adapter_enqueue(uintptr_t tag_op, > +uint16_t cn9k_cpt_crypto_adapter_enqueue(uintptr_t base, > struct rte_crypto_op *op); > __rte_internal > uintptr_t cn9k_cpt_crypto_adapter_dequeue(uintptr_t get_work1); > diff --git a/drivers/event/cnxk/cn10k_worker.c b/drivers/event/cnxk/cn10k_worker.c > index 975a22336a..1ffd48a5ab 100644 > --- a/drivers/event/cnxk/cn10k_worker.c > +++ b/drivers/event/cnxk/cn10k_worker.c > @@ -68,6 +68,5 @@ cn10k_sso_hws_ca_enq(void *port, struct rte_event ev[], uint16_t nb_events) > > RTE_SET_USED(nb_events); > > - return cn10k_cpt_crypto_adapter_enqueue(ws->base + SSOW_LF_GWS_TAG, > - ev->event_ptr); > + return cn10k_cpt_crypto_adapter_enqueue(ws->base, ev->event_ptr); > } > diff --git a/drivers/event/cnxk/cn9k_worker.c b/drivers/event/cnxk/cn9k_worker.c > index a981bc986f..fca1f0dffa 100644 > --- a/drivers/event/cnxk/cn9k_worker.c > +++ b/drivers/event/cnxk/cn9k_worker.c > @@ -128,8 +128,7 @@ cn9k_sso_hws_ca_enq(void *port, struct rte_event ev[], uint16_t nb_events) > > RTE_SET_USED(nb_events); > > - return cn9k_cpt_crypto_adapter_enqueue(ws->base + SSOW_LF_GWS_TAG, > - ev->event_ptr); > + return cn9k_cpt_crypto_adapter_enqueue(ws->base, ev->event_ptr); > } > > uint16_t __rte_hot > @@ -139,6 +138,6 @@ cn9k_sso_hws_dual_ca_enq(void *port, struct rte_event ev[], uint16_t nb_events) > > RTE_SET_USED(nb_events); > > - return cn9k_cpt_crypto_adapter_enqueue( > - dws->base[!dws->vws] + SSOW_LF_GWS_TAG, ev->event_ptr); > + return cn9k_cpt_crypto_adapter_enqueue(dws->base[!dws->vws], > + ev->event_ptr); > } > -- > 2.25.1 >