From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5D6D2A09E4 for ; Wed, 27 Jan 2021 10:57:00 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4E0CE140DDC; Wed, 27 Jan 2021 10:57:00 +0100 (CET) Received: from mail-il1-f171.google.com (mail-il1-f171.google.com [209.85.166.171]) by mails.dpdk.org (Postfix) with ESMTP id E6B35140DBC; Wed, 27 Jan 2021 10:56:56 +0100 (CET) Received: by mail-il1-f171.google.com with SMTP id d6so1179565ilo.6; Wed, 27 Jan 2021 01:56:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=iW6s33STdDrBr8H+5bMmSrNF7CJrSWF6wW9vriMDco8=; b=gzpsJeQIw456cvSiMVeqsNvtbNghyMJSr0P4uMnavrFoViAvF7r54Sqb/9z27l01FL QPnX+p6r7z5pRVCF9CjruL1CflqhoKjjPsdLM+mgeIDBf+FWpxPZ9TclNsePaWjbCVlG WSoySjIoATCkDVh0/eZtaYqWkSGwSihoUkP4RJnIpBFkd4iFPPRRnG4L5UUgpH/qXhXs t7c7UZT8Wgp98Qgi0gYF1Y98djtlxO0SndOOmSMe96Pwizxep/5eqSgsiANpQVbGKHS+ VkYHg7AwPua8K070QkvlqORwE9ZBBlYcaP5lX6DYpOqpwgbjWMgt8J+4KHsrNkmCoEP8 s7Dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=iW6s33STdDrBr8H+5bMmSrNF7CJrSWF6wW9vriMDco8=; b=pjAYdmgB9T0nMu626h2eb5MMZUcRyMxdp6ZcVxEUXHXNxLaViQK/SDFGTmVGeQDKA6 V4xBr0+rLPtT3mBU2RuGAm3IjwxFygg8jMqIwUM0VB2LHQ5y5i3f6Ov1TGRGMUmg10Z9 uiYlQqlqxd90xtAJxxIQmBxjbuUP2FDEA/mpypoLmE7m+EoFCaivItLbkdYj+2l+WprM UYfBPfZ2PGB0DDkiLoHRmTwo6Dv9F+22GYu6yiz/dv5S+Ec5ZWfLXyteTxKYWeObX0Ae nM+cmlWWALUCcGipLUA779RYrORw4L36tFWI93n1kSMOnt2NicG8R4WR56EzDdPY/2HH UY6A== X-Gm-Message-State: AOAM5337eKZ4MOEvIqcCsOLpl4CaODFUHNyzpGFiMwcMbY/xY5D7vExa p8ujzFPYui8al9TYG+y/XggLSW1tvg44QL2LfKA= X-Google-Smtp-Source: ABdhPJxP4bAAfiLE7UPLyxsV4/6Tao5BZli3vbFk6InWgSQaa7cN3if+2DzrU/dl5si4kMmju4L2LmU25Y2bvOr3S6o= X-Received: by 2002:a92:cb0e:: with SMTP id s14mr343494ilo.130.1611741416241; Wed, 27 Jan 2021 01:56:56 -0800 (PST) MIME-Version: 1.0 References: <20210115095821.42721-1-joyce.kong@arm.com> In-Reply-To: From: Jerin Jacob Date: Wed, 27 Jan 2021 15:26:39 +0530 Message-ID: To: Ruifeng Wang Cc: Joyce Kong , "jerinj@marvell.com" , "david.marchand@redhat.com" , Honnappa Nagarahalli , "dev@dpdk.org" , nd , "stable@dpdk.org" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Subject: Re: [dpdk-stable] [dpdk-dev] [PATCH v1] eal/arm: fix gcc build for 128-bit atomic compare exchange X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" On Wed, Jan 27, 2021 at 9:06 AM Ruifeng Wang wrote: > > > -----Original Message----- > > From: Joyce Kong > > Sent: Friday, January 15, 2021 5:58 PM > > To: jerinj@marvell.com; david.marchand@redhat.com; Ruifeng Wang > > ; Honnappa Nagarahalli > > > > Cc: dev@dpdk.org; nd ; stable@dpdk.org > > Subject: [PATCH v1] eal/arm: fix gcc build for 128-bit atomic compare > > exchange > > > > Compiling with "meson build -Dbuildtype=3Ddebug --cross-file > > config/arm/arm64_thunderx2_linux_gcc" shows the warnings "function > > Issue can be reproduced with the posted command. But it is not specific t= o ThunderX2 platform. > It is reproducible on any platform that has LSE extension when building w= ith 'buildtype=3Ddebug'. > > Reviewed-by: Ruifeng Wang Acked-by: Jerin Jacob > > > returns an aggregate [-Waggregate-return]": > > ../../dpdk/lib/librte_eal/arm/include/rte_atomic_64.h: In function > > =E2=80=98__cas_128_relaxed=E2=80=99: > > ../../dpdk/lib/librte_eal/arm/include/rte_atomic_64.h:81:20: > > error: function returns an aggregate [-Werror=3Daggregate-return] > > __ATOMIC128_CAS_OP(__cas_128_relaxed, "casp") > > ^~~~~~~~~~~~~~~~~ > > > > Fix the compiling issue by defining __ATOMIC128_CAS_OP as a void functi= on > > and passing the address pointer into it. > > > > Fixes: 7e2c3e17fe2c ("eal/arm64: add 128-bit atomic compare exchange") > > Cc: stable@dpdk.org > > > > Signed-off-by: Joyce Kong > > --- > > lib/librte_eal/arm/include/rte_atomic_64.h | 28 +++++++++++----------- > > 1 file changed, 14 insertions(+), 14 deletions(-) > > > > diff --git a/lib/librte_eal/arm/include/rte_atomic_64.h > > b/lib/librte_eal/arm/include/rte_atomic_64.h > > index 467d32a45..fa6f334c0 100644 > > --- a/lib/librte_eal/arm/include/rte_atomic_64.h > > +++ b/lib/librte_eal/arm/include/rte_atomic_64.h > > @@ -53,15 +53,15 @@ rte_atomic_thread_fence(int memorder) #endif > > > > #define __ATOMIC128_CAS_OP(cas_op_name, op_string) = \ > > -static __rte_noinline rte_int128_t = \ > > -cas_op_name(rte_int128_t *dst, rte_int128_t old, rte_int128_t updated) > > \ > > +static __rte_noinline void = \ > > +cas_op_name(rte_int128_t *dst, rte_int128_t *old, rte_int128_t updated= ) > > \ > > { = \ > > /* caspX instructions register pair must start from even-numbered > > * register at operand 1. > > * So, specify registers for local variables here. > > */ = \ > > - register uint64_t x0 __asm("x0") =3D (uint64_t)old.val[0]; = \ > > - register uint64_t x1 __asm("x1") =3D (uint64_t)old.val[1]; = \ > > + register uint64_t x0 __asm("x0") =3D (uint64_t)old->val[0]; = \ > > + register uint64_t x1 __asm("x1") =3D (uint64_t)old->val[1]; = \ > > register uint64_t x2 __asm("x2") =3D (uint64_t)updated.val[0]; = \ > > register uint64_t x3 __asm("x3") =3D (uint64_t)updated.val[1]; = \ > > asm volatile( = \ > > @@ -73,9 +73,8 @@ cas_op_name(rte_int128_t *dst, rte_int128_t old, > > rte_int128_t updated) \ > > [upd1] "r" (x3), = \ > > [dst] "r" (dst) = \ > > : "memory"); = \ > > - old.val[0] =3D x0; = \ > > - old.val[1] =3D x1; = \ > > - return old; = \ > > + old->val[0] =3D x0; = \ > > + old->val[1] =3D x1; = \ > > } > > > > __ATOMIC128_CAS_OP(__cas_128_relaxed, "casp") @@ -113,13 +112,14 > > @@ rte_atomic128_cmp_exchange(rte_int128_t *dst, rte_int128_t *exp, > > > > #if defined(__ARM_FEATURE_ATOMICS) || > > defined(RTE_ARM_FEATURE_ATOMICS) > > if (success =3D=3D __ATOMIC_RELAXED) > > - old =3D __cas_128_relaxed(dst, expected, desired); > > + __cas_128_relaxed(dst, exp, desired); > > else if (success =3D=3D __ATOMIC_ACQUIRE) > > - old =3D __cas_128_acquire(dst, expected, desired); > > + __cas_128_acquire(dst, exp, desired); > > else if (success =3D=3D __ATOMIC_RELEASE) > > - old =3D __cas_128_release(dst, expected, desired); > > + __cas_128_release(dst, exp, desired); > > else > > - old =3D __cas_128_acq_rel(dst, expected, desired); > > + __cas_128_acq_rel(dst, exp, desired); > > + old =3D *exp; > > #else > > #define __HAS_ACQ(mo) ((mo) !=3D __ATOMIC_RELAXED && (mo) !=3D > > __ATOMIC_RELEASE) #define __HAS_RLS(mo) ((mo) =3D=3D > > __ATOMIC_RELEASE || (mo) =3D=3D __ATOMIC_ACQ_REL || \ @@ -183,12 > > +183,12 @@ rte_atomic128_cmp_exchange(rte_int128_t *dst, rte_int128_t > > *exp, #undef __STORE_128 > > > > } while (unlikely(ret)); > > -#endif > > > > - /* Unconditionally updating expected removes an 'if' statement. > > - * expected should already be in register if not in the cache. > > + /* Unconditionally updating the value of exp removes an 'if' > > statement. > > + * The value of exp should already be in register if not in the c= ache. > > */ > > *exp =3D old; > > +#endif > > > > return (old.int128 =3D=3D expected.int128); } > > -- > > 2.30.0 >