From: Jerin Jacob <jerinjacobk@gmail.com> To: Satheesh Paul <psatheesh@marvell.com> Cc: Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao <skoteshwar@marvell.com>, dpdk-dev <dev@dpdk.org>, dpdk stable <stable@dpdk.org> Subject: Re: [dpdk-dev] [PATCH] common/cnxk: fix channel number setting in MCAM entries Date: Mon, 13 Jun 2022 12:56:47 +0530 Message-ID: <CALBAE1P++6N4pD6c-b5W1fYhUT=OewHLHxNcHAGDUGVvu=fwEQ@mail.gmail.com> (raw) In-Reply-To: <20220502084730.609989-1-psatheesh@marvell.com> On Mon, May 2, 2022 at 2:17 PM <psatheesh@marvell.com> wrote: > > From: Satheesh Paul <psatheesh@marvell.com> > > Adding changes to accommodate the following requirements > while masking the channel number. > 1. For CN10K device, channel number should not be masked > for first pass rules with RTE_FLOW_ACTION_TYPE_SECURITY > action. And channel number should be masked for all > other flow rules. > 2. For CN9K device channel number should not be masked. > > Fixes: 29dcc20985 ("common/cnxk: support for CPT second pass flow rules") Not correct. Updated as Fixes: 4968b362b639 ("common/cnxk: support CPT second pass flow rules") > Cc: stable@dpdk.org > > Signed-off-by: Satheesh Paul <psatheesh@marvell.com> > Reviewed-by: Kiran Kumar Kokkilagadda <kirankumark@marvell.com> Updated as Reviewed-by: Kiran Kumar K <kirankumark@marvell.com> Please check this in future patches, Applied to dpdk-next-net-mrvl/for-next-net. Thanks > --- > drivers/common/cnxk/roc_npc_mcam.c | 30 ++++++++++++++++++------------ > 1 file changed, 18 insertions(+), 12 deletions(-) > > diff --git a/drivers/common/cnxk/roc_npc_mcam.c b/drivers/common/cnxk/roc_npc_mcam.c > index bccbaaa51f..0ae58da0ba 100644 > --- a/drivers/common/cnxk/roc_npc_mcam.c > +++ b/drivers/common/cnxk/roc_npc_mcam.c > @@ -508,19 +508,25 @@ npc_mcam_set_channel(struct roc_npc_flow *flow, > req->entry_data.kw_mask[0] &= ~(GENMASK(11, 0)); > flow->mcam_data[0] &= ~(GENMASK(11, 0)); > flow->mcam_mask[0] &= ~(GENMASK(11, 0)); > + chan = channel; > + mask = chan_mask; > > - if (is_second_pass) { > - chan = (channel | NIX_CHAN_CPT_CH_START); > - mask = (chan_mask | NIX_CHAN_CPT_CH_START); > - } else { > - /* > - * Clear bits 10 & 11 corresponding to CPT > - * channel. By default, rules should match > - * both first pass packets and second pass > - * packets from CPT. > - */ > - chan = (channel & NIX_CHAN_CPT_X2P_MASK); > - mask = (chan_mask & NIX_CHAN_CPT_X2P_MASK); > + if (roc_model_runtime_is_cn10k()) { > + if (is_second_pass) { > + chan = (channel | NIX_CHAN_CPT_CH_START); > + mask = (chan_mask | NIX_CHAN_CPT_CH_START); > + } else { > + if (!(flow->npc_action & NIX_RX_ACTIONOP_UCAST_IPSEC)) { > + /* > + * Clear bits 10 & 11 corresponding to CPT > + * channel. By default, rules should match > + * both first pass packets and second pass > + * packets from CPT. > + */ > + chan = (channel & NIX_CHAN_CPT_X2P_MASK); > + mask = (chan_mask & NIX_CHAN_CPT_X2P_MASK); > + } > + } > } > > req->entry_data.kw[0] |= (uint64_t)chan; > -- > 2.25.4 >
prev parent reply other threads:[~2022-06-13 7:27 UTC|newest] Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-05-02 8:47 psatheesh 2022-06-13 7:26 ` Jerin Jacob [this message]
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