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From: Suanming Mou <suanmingm@nvidia.com>
To: Dariusz Sosnowski <dsosnowski@nvidia.com>,
	Matan Azrad <matan@nvidia.com>,
	 Slava Ovsiienko <viacheslavo@nvidia.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>,
	"stable@dpdk.org" <stable@dpdk.org>, Ori Kam <orika@nvidia.com>
Subject: RE: [PATCH 1/2] net/mlx5: fix egress group translation in HWS
Date: Wed, 8 Mar 2023 03:04:01 +0000	[thread overview]
Message-ID: <CO6PR12MB539612C7A4CF751D6A45427DC1B49@CO6PR12MB5396.namprd12.prod.outlook.com> (raw)
In-Reply-To: <20230225201810.10838-2-dsosnowski@nvidia.com>



> -----Original Message-----
> From: Dariusz Sosnowski <dsosnowski@nvidia.com>
> Sent: Sunday, February 26, 2023 4:18 AM
> To: Matan Azrad <matan@nvidia.com>; Slava Ovsiienko
> <viacheslavo@nvidia.com>
> Cc: dev@dpdk.org; stable@dpdk.org; Ori Kam <orika@nvidia.com>
> Subject: [PATCH 1/2] net/mlx5: fix egress group translation in HWS
> 
> With HW Steering enabled creating egress template tables and egress flow rules
> on E-Switch setups is allowed.
> To enable it, PMD creates a set of default egress flow rules responsible for:
> 
> - Storing representor ID (vport tag is used) in HW register.
>   This is used for traffic source identification.
> - Copying software metadata to proper HW register to allow
>   preserving metadata across domains.
> 
> Structure of these flow rules and whether they are inserted depend on the
> device configuration.
> There are the following cases:
> 
> 1. repr_matching=1 and dv_xmeta_en=4
>    - An egress flow rule in group 0 is created for each Tx queue;
>    - Flow rule matching SQ number - fills unused REG_C_0 bits
>      with vport tag, copies REG_A to REG_C_1 and jumps to group 1.
> 2. repr_matching=1 and dv_xmeta_en=0
>    - An egress flow rule in group 0 is created for each Tx queue;
>    - Flow rule matching SQ number - fills unused REG_C_0 bits
>      with vport tag and jumps to group 1.
> 3. repr_matching=0 and dv_xmeta_en=4
>    - A single egress flow rule in group 0 is created;
>    - Flow rule matches all E-Switch manager TX traffic,
>      copies REG_A to REG_C and jumps to group 1.
> 4. repr_matching=0 and dv_xmeta_en=0 - no default flow rules are added.
> 
> When default egress flow rules are required, they are inserted in group 0 and
> this group is reserved for PMD purposes.
> User created template tables must be created in higher groups.
> As a result, on template table creation PMD is translating the provided group
> (incrementing it in that case).
> 
> Before this patch, a condition used to check if translation of egress flow group is
> needed was incorrect. It did not allow translation if both representor matching
> AND extended metadata mode were enabled.
> 
> This patch fixes this condition - translation is allowed if and only if representor
> matching OR extended metadata mode is enabled.
> 
> Fixes: 483181f7b6dd ("net/mlx5: support device control of representor
> matching")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
> Acked-by: Ori Kam <orika@nvidia.com>
Acked-by: Suanming Mou <suanmingm@nvidia.com>


  reply	other threads:[~2023-03-08  3:04 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-25 20:18 [PATCH 0/2] net/mlx5: fix representor matching Dariusz Sosnowski
2023-02-25 20:18 ` [PATCH 1/2] net/mlx5: fix egress group translation in HWS Dariusz Sosnowski
2023-03-08  3:04   ` Suanming Mou [this message]
2023-02-25 20:18 ` [PATCH 2/2] net/mlx5: fix isolated mode when repr matching is disabled Dariusz Sosnowski
2023-03-08  3:04   ` Suanming Mou
2023-03-19 15:32 ` [PATCH 0/2] net/mlx5: fix representor matching Matan Azrad
2023-03-19 17:26 ` Raslan Darawsheh

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