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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DB3PR0502MB4028.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5ad7546f-ddd7-4cda-ea07-08d82bd254cc X-MS-Exchange-CrossTenant-originalarrivaltime: 19 Jul 2020 10:56:03.7617 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 3mqPxoFM6dGfavmmv1a5jqGvjIzBmnM9TkMB/A4c1HENzUOLAGNVvFDWFIjaBcMdZqF+TY9iqLMd7EAfJwc+ng== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB7PR05MB4299 Subject: Re: [dpdk-stable] [PATCH] common/mlx5: fix CPU detection for PCI relaxed ordering X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" From: Thomas Monjalon > The detection of the CPU was done in a constructor and shared in a global > variable. >=20 > This variable may not be visible in the net PMD because it was not export= ed > as part of the .map file. Can you explain exactly when it is not visible? > It is fixed by exporting a function, which is cleaner than a variable. Can you explain why? We have classic example - rte_eth_devices. > By checking the CPU only at the first call of the function, doing the che= ck in a > constructor becomes useless. Yes, but why not to do it in constructor? this variable is initialized only= once and doesn't depend in any parameter. > Note: the priority of the constructor was probably irrelevant. >=20 > At the same time, the comments are reworded or dropped if useless. >=20 > Fixes: 4c204fe5e5d2 ("common/mlx5: disable relaxed ordering in unsuitable > CPUs") > Cc: shirik@mellanox.com > Cc: stable@dpdk.org >=20 > Signed-off-by: Thomas Monjalon > --- > drivers/common/mlx5/linux/mlx5_common_verbs.c | 2 +- > drivers/common/mlx5/mlx5_common.c | 53 ++++++++----------- > drivers/common/mlx5/mlx5_common.h | 4 +- > .../common/mlx5/rte_common_mlx5_version.map | 2 + > drivers/net/mlx5/mlx5_flow_dv.c | 2 +- > 5 files changed, 28 insertions(+), 35 deletions(-) >=20 > diff --git a/drivers/common/mlx5/linux/mlx5_common_verbs.c > b/drivers/common/mlx5/linux/mlx5_common_verbs.c > index a2fc7a36bd..31ac20fe09 100644 > --- a/drivers/common/mlx5/linux/mlx5_common_verbs.c > +++ b/drivers/common/mlx5/linux/mlx5_common_verbs.c > @@ -55,7 +55,7 @@ mlx5_common_verbs_reg_mr(void *pd, void *addr, > size_t length, > memset(pmd_mr, 0, sizeof(*pmd_mr)); > ibv_mr =3D mlx5_glue->reg_mr(pd, addr, length, > IBV_ACCESS_LOCAL_WRITE | > - (haswell_broadwell_cpu ? 0 : > + (mlx5_cpu_is_haswell_broadwell() ? 0 : > IBV_ACCESS_RELAXED_ORDERING)); > if (!ibv_mr) > return -1; > diff --git a/drivers/common/mlx5/mlx5_common.c > b/drivers/common/mlx5/mlx5_common.c > index 693e2c68c8..7232d5131d 100644 > --- a/drivers/common/mlx5/mlx5_common.c > +++ b/drivers/common/mlx5/mlx5_common.c > @@ -20,8 +20,6 @@ int mlx5_common_logtype; const struct mlx5_glue > *mlx5_glue; #endif >=20 > -uint8_t haswell_broadwell_cpu; > - > static int > mlx5_class_check_handler(__rte_unused const char *key, const char > *value, > void *opaque) > @@ -59,19 +57,8 @@ mlx5_class_get(struct rte_devargs *devargs) } >=20 >=20 > -/* In case this is an x86_64 intel processor to check if > - * we should use relaxed ordering. > - */ > #ifdef RTE_ARCH_X86_64 > -/** > - * This function returns processor identification and feature informatio= n > - * into the registers. > - * > - * @param eax, ebx, ecx, edx > - * Pointers to the registers that will hold cpu information. > - * @param level > - * The main category of information returned. > - */ > +/* Processor identification and feature information filled in > +registers. */ > static inline void mlx5_cpu_id(unsigned int level, > unsigned int *eax, unsigned int *ebx, > unsigned int *ecx, unsigned int *edx) @@ - > 97,17 +84,7 @@ RTE_INIT_PRIO(mlx5_glue_init, CLASS) > mlx5_glue_constructor(); > } >=20 > -/** > - * This function is responsible of initializing the variable > - * haswell_broadwell_cpu by checking if the cpu is intel > - * and reading the data returned from mlx5_cpu_id(). > - * since haswell and broadwell cpus don't have improved performance > - * when using relaxed ordering we want to check the cpu type before > - * before deciding whether to enable RO or not. > - * if the cpu is haswell or broadwell the variable will be set to 1 > - * otherwise it will be 0. > - */ > -RTE_INIT_PRIO(mlx5_is_haswell_broadwell_cpu, LOG) > +static bool mlx5_x86_is_haswell_broadwell(void) > { > #ifdef RTE_ARCH_X86_64 > unsigned int broadwell_models[4] =3D {0x3d, 0x47, 0x4F, 0x56}; @@ - > 125,8 +102,7 @@ RTE_INIT_PRIO(mlx5_is_haswell_broadwell_cpu, LOG) > vendor =3D ebx; > max_level =3D eax; > if (max_level < 1) { > - haswell_broadwell_cpu =3D 0; > - return; > + return false; > } > mlx5_cpu_id(1, &eax, &ebx, &ecx, &edx); > model =3D (eax >> 4) & 0x0f; > @@ -140,18 +116,31 @@ RTE_INIT_PRIO(mlx5_is_haswell_broadwell_cpu, > LOG) > if (brand_id =3D=3D 0 && family =3D=3D 0x6) { > for (i =3D 0; i < RTE_DIM(broadwell_models); i++) > if (model =3D=3D broadwell_models[i]) { > - haswell_broadwell_cpu =3D 1; > - return; > + return true; > } > for (i =3D 0; i < RTE_DIM(haswell_models); i++) > if (model =3D=3D haswell_models[i]) { > - haswell_broadwell_cpu =3D 1; > - return; > + return true; > } > } > } > #endif > - haswell_broadwell_cpu =3D 0; > + return false; > +} > + > +/* > + * Check if the CPU is Intel Haswell or Broadwell, > + * because PCI relaxed ordering has no performance benefit with these > CPUs. > + */ > +bool mlx5_cpu_is_haswell_broadwell(void) > +{ > + static bool haswell_broadwell_cpu; > + static bool once =3D false; > + > + if (once) > + return haswell_broadwell_cpu; > + once =3D true; > + return haswell_broadwell_cpu =3D mlx5_x86_is_haswell_broadwell(); > } >=20 > /** > diff --git a/drivers/common/mlx5/mlx5_common.h > b/drivers/common/mlx5/mlx5_common.h > index 2851507058..d453e0b3d8 100644 > --- a/drivers/common/mlx5/mlx5_common.h > +++ b/drivers/common/mlx5/mlx5_common.h > @@ -243,6 +243,9 @@ struct mlx5_klm { >=20 > LIST_HEAD(mlx5_dbr_page_list, mlx5_devx_dbr_page); >=20 > +__rte_internal > +bool mlx5_cpu_is_haswell_broadwell(void); > + > __rte_internal > enum mlx5_class mlx5_class_get(struct rte_devargs *devargs); > __rte_internal @@ -255,6 +258,5 @@ int64_t mlx5_get_dbr(void *ctx, struc= t > mlx5_dbr_page_list *head, __rte_internal int32_t mlx5_release_dbr(struc= t > mlx5_dbr_page_list *head, uint32_t umem_id, > uint64_t offset); > -extern uint8_t haswell_broadwell_cpu; >=20 > #endif /* RTE_PMD_MLX5_COMMON_H_ */ > diff --git a/drivers/common/mlx5/rte_common_mlx5_version.map > b/drivers/common/mlx5/rte_common_mlx5_version.map > index ae57ebdba5..501b9fff3b 100644 > --- a/drivers/common/mlx5/rte_common_mlx5_version.map > +++ b/drivers/common/mlx5/rte_common_mlx5_version.map > @@ -6,6 +6,8 @@ INTERNAL { > mlx5_common_verbs_reg_mr; > mlx5_common_verbs_dereg_mr; >=20 > + mlx5_cpu_is_haswell_broadwell; > + > mlx5_create_mr_ext; >=20 > mlx5_dev_to_pci_addr; > diff --git a/drivers/net/mlx5/mlx5_flow_dv.c > b/drivers/net/mlx5/mlx5_flow_dv.c index 8b5b6838fa..f1109ae095 100644 > --- a/drivers/net/mlx5/mlx5_flow_dv.c > +++ b/drivers/net/mlx5/mlx5_flow_dv.c > @@ -4201,7 +4201,7 @@ flow_dv_create_counter_stat_mem_mng(struct > rte_eth_dev *dev, int raws_n) > mkey_attr.klm_num =3D 0; > if (priv->config.hca_attr.relaxed_ordering_write && > priv->config.hca_attr.relaxed_ordering_read && > - !haswell_broadwell_cpu) > + !mlx5_cpu_is_haswell_broadwell()) > mkey_attr.relaxed_ordering =3D 1; > mem_mng->dm =3D mlx5_devx_cmd_mkey_create(sh->ctx, > &mkey_attr); > if (!mem_mng->dm) { > -- > 2.27.0