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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(4636009)(396003)(39850400004)(136003)(376002)(346002)(46966005)(9686003)(54906003)(83380400001)(2906002)(110136005)(82740400003)(316002)(70586007)(70206006)(55016002)(478600001)(8936002)(47076004)(81166007)(7696005)(8676002)(356005)(33656002)(186003)(26005)(450100002)(4326008)(36906005)(53546011)(82310400003)(6506007)(336012)(52536014)(5660300002)(86362001); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2020 02:34:20.4268 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1a7e9f76-7d51-443b-0c85-08d86bfbd3ae X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT016.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR08MB4674 Subject: Re: [dpdk-stable] [PATCH 2/2] lib/ethdev: fix memory ordering for call back functions X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" > -----Original Message----- > From: Honnappa Nagarahalli > Sent: Friday, October 2, 2020 8:07 AM > To: dev@dpdk.org; Honnappa Nagarahalli > ; Phil Yang ; > thomas@monjalon.net; arybchenko@solarflare.com; ferruh.yigit@intel.com > Cc: abhinandan.gujjar@intel.com; nd ; > bruce.richardson@intel.com; john.mcnamara@intel.com; > reshma.pattan@intel.com; stable@dpdk.org > Subject: [PATCH 2/2] lib/ethdev: fix memory ordering for call back functi= ons >=20 > Call back functions are registered on the control plane. They > are accessed from the data plane. Hence, correct memory orderings > should be used to avoid race conditions. >=20 > Fixes: 4dc294158cac ("ethdev: support optional Rx and Tx callbacks") > Fixes: c8231c63ddcb ("ethdev: insert Rx callback as head of list") > Cc: bruce.richardson@intel.com > Cc: john.mcnamara@intel.com > Cc: reshma.pattan@intel.com > Cc: stable@dpdk.org >=20 > Signed-off-by: Honnappa Nagarahalli > Reviewed-by: Ola Liljedahl Reviewed-by: Phil Yang > --- > lib/librte_ethdev/rte_ethdev.c | 28 +++++++++++++++++++++------ > lib/librte_ethdev/rte_ethdev.h | 35 ++++++++++++++++++++++++++------- > - > 2 files changed, 49 insertions(+), 14 deletions(-) >=20 > diff --git a/lib/librte_ethdev/rte_ethdev.c b/lib/librte_ethdev/rte_ethde= v.c > index 59a41c07f..d89fcdc77 100644 > --- a/lib/librte_ethdev/rte_ethdev.c > +++ b/lib/librte_ethdev/rte_ethdev.c > @@ -4486,12 +4486,20 @@ rte_eth_add_rx_callback(uint16_t port_id, > uint16_t queue_id, > rte_eth_devices[port_id].post_rx_burst_cbs[queue_id]; >=20 > if (!tail) { > - rte_eth_devices[port_id].post_rx_burst_cbs[queue_id] =3D cb; > + /* Stores to cb->fn and cb->param should complete before > + * cb is visible to data plane. > + */ > + __atomic_store_n( > + > &rte_eth_devices[port_id].post_rx_burst_cbs[queue_id], > + cb, __ATOMIC_RELEASE); >=20 > } else { > while (tail->next) > tail =3D tail->next; > - tail->next =3D cb; > + /* Stores to cb->fn and cb->param should complete before > + * cb is visible to data plane. > + */ > + __atomic_store_n(&tail->next, cb, __ATOMIC_RELEASE); > } > rte_spinlock_unlock(&rte_eth_rx_cb_lock); >=20 > @@ -4576,12 +4584,20 @@ rte_eth_add_tx_callback(uint16_t port_id, > uint16_t queue_id, > rte_eth_devices[port_id].pre_tx_burst_cbs[queue_id]; >=20 > if (!tail) { > - rte_eth_devices[port_id].pre_tx_burst_cbs[queue_id] =3D cb; > + /* Stores to cb->fn and cb->param should complete before > + * cb is visible to data plane. > + */ > + __atomic_store_n( > + > &rte_eth_devices[port_id].pre_tx_burst_cbs[queue_id], > + cb, __ATOMIC_RELEASE); >=20 > } else { > while (tail->next) > tail =3D tail->next; > - tail->next =3D cb; > + /* Stores to cb->fn and cb->param should complete before > + * cb is visible to data plane. > + */ > + __atomic_store_n(&tail->next, cb, __ATOMIC_RELEASE); > } > rte_spinlock_unlock(&rte_eth_tx_cb_lock); >=20 > @@ -4612,7 +4628,7 @@ rte_eth_remove_rx_callback(uint16_t port_id, > uint16_t queue_id, > cb =3D *prev_cb; > if (cb =3D=3D user_cb) { > /* Remove the user cb from the callback list. */ > - *prev_cb =3D cb->next; > + __atomic_store_n(prev_cb, cb->next, > __ATOMIC_RELAXED); > ret =3D 0; > break; > } > @@ -4646,7 +4662,7 @@ rte_eth_remove_tx_callback(uint16_t port_id, > uint16_t queue_id, > cb =3D *prev_cb; > if (cb =3D=3D user_cb) { > /* Remove the user cb from the callback list. */ > - *prev_cb =3D cb->next; > + __atomic_store_n(prev_cb, cb->next, > __ATOMIC_RELAXED); > ret =3D 0; > break; > } > diff --git a/lib/librte_ethdev/rte_ethdev.h b/lib/librte_ethdev/rte_ethde= v.h > index 70295d7ab..d810e3e38 100644 > --- a/lib/librte_ethdev/rte_ethdev.h > +++ b/lib/librte_ethdev/rte_ethdev.h > @@ -3734,7 +3734,8 @@ struct rte_eth_rxtx_callback; > * The callback function > * @param user_param > * A generic pointer parameter which will be passed to each invocation= of > the > - * callback function on this port and queue. > + * callback function on this port and queue. Inter-thread synchronizat= ion > + * of any user data changes is the responsibility of the user. > * > * @return > * NULL on error. > @@ -3763,7 +3764,8 @@ rte_eth_add_rx_callback(uint16_t port_id, uint16_t > queue_id, > * The callback function > * @param user_param > * A generic pointer parameter which will be passed to each invocation= of > the > - * callback function on this port and queue. > + * callback function on this port and queue. Inter-thread synchronizat= ion > + * of any user data changes is the responsibility of the user. > * > * @return > * NULL on error. > @@ -3791,7 +3793,8 @@ rte_eth_add_first_rx_callback(uint16_t port_id, > uint16_t queue_id, > * The callback function > * @param user_param > * A generic pointer parameter which will be passed to each invocation= of > the > - * callback function on this port and queue. > + * callback function on this port and queue. Inter-thread synchronizat= ion > + * of any user data changes is the responsibility of the user. > * > * @return > * NULL on error. > @@ -3816,7 +3819,9 @@ rte_eth_add_tx_callback(uint16_t port_id, uint16_t > queue_id, > * on that queue. > * > * - After a short delay - where the delay is sufficient to allow any > - * in-flight callbacks to complete. > + * in-flight callbacks to complete. Alternately, the RCU mechanism can= be > + * used to detect when data plane threads have ceased referencing the > + * callback memory. > * > * @param port_id > * The port identifier of the Ethernet device. > @@ -3849,7 +3854,9 @@ int rte_eth_remove_rx_callback(uint16_t port_id, > uint16_t queue_id, > * on that queue. > * > * - After a short delay - where the delay is sufficient to allow any > - * in-flight callbacks to complete. > + * in-flight callbacks to complete. Alternately, the RCU mechanism can= be > + * used to detect when data plane threads have ceased referencing the > + * callback memory. > * > * @param port_id > * The port identifier of the Ethernet device. > @@ -4510,10 +4517,16 @@ rte_eth_rx_burst(uint16_t port_id, uint16_t > queue_id, > rx_pkts, nb_pkts); >=20 > #ifdef RTE_ETHDEV_RXTX_CALLBACKS > - if (unlikely(dev->post_rx_burst_cbs[queue_id] !=3D NULL)) { > - struct rte_eth_rxtx_callback *cb =3D > - dev->post_rx_burst_cbs[queue_id]; > + /* __ATOMIC_RELEASE memory order was used when the > + * call back was inserted into the list. > + * Since there is a clear dependency between loading > + * cb and cb->fn/cb->next, __ATOMIC_ACQUIRE memory order is > + * not required. > + */ > + struct rte_eth_rxtx_callback *cb =3D > + dev->post_rx_burst_cbs[queue_id]; >=20 > + if (unlikely(cb !=3D NULL)) { > do { > nb_rx =3D cb->fn.rx(port_id, queue_id, rx_pkts, nb_rx, > nb_pkts, cb->param); > @@ -4775,6 +4788,12 @@ rte_eth_tx_burst(uint16_t port_id, uint16_t > queue_id, > #endif >=20 > #ifdef RTE_ETHDEV_RXTX_CALLBACKS > + /* __ATOMIC_RELEASE memory order was used when the > + * call back was inserted into the list. > + * Since there is a clear dependency between loading > + * cb and cb->fn/cb->next, __ATOMIC_ACQUIRE memory order is > + * not required. > + */ > struct rte_eth_rxtx_callback *cb =3D dev- > >pre_tx_burst_cbs[queue_id]; >=20 > if (unlikely(cb !=3D NULL)) { > -- > 2.17.1