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Tue, 27 Sep 2022 21:03:58 +0000 From: Honnappa Nagarahalli To: Slava Ovsiienko , "dev@dpdk.org" , Ruifeng Wang , Matan Azrad , Shahaf Shuler CC: nd , Matan Azrad , "stable@dpdk.org" , nd Subject: RE: [PATCH v2] net/mlx5: use just sufficient barrier for Arm platforms Thread-Topic: [PATCH v2] net/mlx5: use just sufficient barrier for Arm platforms Thread-Index: AQHY0js6kBq/o7BFf0Kgf4d3XmoqKq3zvuag Date: Tue, 27 Sep 2022 21:03:58 +0000 Message-ID: References: <20210606164948.35997-1-honnappa.nagarahalli@arm.com> <20220830200038.1694160-1-honnappa.nagarahalli@arm.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ts-tracking-id: 6E0EA0CD6C273B499753C8B66A7959EE.0 x-checkrecipientchecked: true Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; x-ms-traffictypediagnostic: DBAPR08MB5814:EE_|DBBPR08MB6057:EE_|VE1EUR03FT035:EE_|GV2PR08MB8461:EE_ X-MS-Office365-Filtering-Correlation-Id: 64c22f48-c23f-426d-c2dd-08daa0cbd04c x-checkrecipientrouted: true nodisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; 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CAT:NONE; SFS:(13230022)(4636009)(396003)(346002)(376002)(136003)(39860400002)(451199015)(36840700001)(46966006)(40470700004)(33656002)(55016003)(82310400005)(40480700001)(26005)(47076005)(41300700001)(336012)(7696005)(83380400001)(186003)(9686003)(8936002)(52536014)(356005)(2906002)(86362001)(40460700003)(5660300002)(110136005)(54906003)(316002)(70206006)(8676002)(36860700001)(966005)(6506007)(70586007)(478600001)(82740400003)(450100002)(4326008)(81166007)(53546011); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Sep 2022 21:04:05.8280 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 64c22f48-c23f-426d-c2dd-08daa0cbd04c X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT035.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV2PR08MB8461 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org >=20 > Hi, Honnappa Hi Slava, thanks for the feedback. >=20 > We discussed the barrier here: > http://patches.dpdk.org/project/dpdk/patch/20210606164948.35997-1- > honnappa.nagarahalli@arm.com/ Yes, I have changed the patch according to the discussion. i.e. barrier is = needed, but different (inner sharable domain) barrier is required. >=20 > (BTW, it is good practice to keep the reference to previous patch version= s > below Commit Message of the next ones). >=20 > This barrier is not about compiler ordering, it is about external HW agen= t > memory action completions. > So, I'm not sure the rte_atomic_thread_fence() is safe for x86 - patch im= pacts > x86 as well. The earlier barrier 'rte_io_rmb()', resolves to a compiler barrier on x86 [= 1]. The rte_atomic_thread_fence(__ATOMIC_ACQUIRE) on x86 also acts as a com= piler barrier. So, there is no change for x86. [1] https://github.com/DPDK/dpdk/blob/main/lib/eal/x86/include/rte_atomic.h= #L80 >=20 > With best regards, > Slava >=20 > > -----Original Message----- > > From: Honnappa Nagarahalli > > Sent: Tuesday, August 30, 2022 23:01 > > To: dev@dpdk.org; honnappa.nagarahalli@arm.com; > ruifeng.wang@arm.com; > > Matan Azrad ; Shahaf Shuler ; > > Slava Ovsiienko > > Cc: nd@arm.com; Matan Azrad ; stable@dpdk.org > > Subject: [PATCH v2] net/mlx5: use just sufficient barrier for Arm > > platforms > > > > cqe->op_own indicates if the CQE is owned by the NIC. The rest of > > the fields in CQE should be read only after op_own is read. On Arm > > platforms using "dmb ishld" is sufficient to enforce this. > > > > Fixes: 88c0733535d6 ("net/mlx5: extend Rx completion with error > > handling") > > Cc: matan@mellanox.com > > Cc: stable@dpdk.org > > > > Signed-off-by: Honnappa Nagarahalli > > Reviewed-by: Ruifeng Wang > > --- > > drivers/common/mlx5/mlx5_common.h | 6 +++++- > > 1 file changed, 5 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/common/mlx5/mlx5_common.h > > b/drivers/common/mlx5/mlx5_common.h > > index 5028a05b49..ac2e85b15f 100644 > > --- a/drivers/common/mlx5/mlx5_common.h > > +++ b/drivers/common/mlx5/mlx5_common.h > > @@ -195,7 +195,11 @@ check_cqe(volatile struct mlx5_cqe *cqe, const > > uint16_t cqes_n, > > > > if (unlikely((op_owner !=3D (!!(idx))) || (op_code =3D=3D > > MLX5_CQE_INVALID))) > > return MLX5_CQE_STATUS_HW_OWN; > > - rte_io_rmb(); > > + /* Prevent speculative reading of other fields in CQE until > > + * CQE is valid. > > + */ > > + rte_atomic_thread_fence(__ATOMIC_ACQUIRE); > > + > > if (unlikely(op_code =3D=3D MLX5_CQE_RESP_ERR || > > op_code =3D=3D MLX5_CQE_REQ_ERR)) > > return MLX5_CQE_STATUS_ERR; > > -- > > 2.17.1