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From: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
To: Ferruh Yigit <ferruh.yigit@intel.com>,
	Ruifeng Wang <Ruifeng.Wang@arm.com>,
	"dev@dpdk.org" <dev@dpdk.org>
Cc: "beilei.xing@intel.com" <beilei.xing@intel.com>,
	"qi.z.zhang@intel.com" <qi.z.zhang@intel.com>,
	"bruce.richardson@intel.com" <bruce.richardson@intel.com>,
	"jerinj@marvell.com" <jerinj@marvell.com>,
	"hemant.agrawal@nxp.com" <hemant.agrawal@nxp.com>,
	"drc@linux.vnet.ibm.com" <drc@linux.vnet.ibm.com>,
	"stable@dpdk.org" <stable@dpdk.org>, nd <nd@arm.com>,
	"humin29@huawei.com" <humin29@huawei.com>, nd <nd@arm.com>
Subject: Re: [dpdk-stable] [PATCH v2 2/2] net/i40e: fix risk in Rx descriptor read in scalar path
Date: Wed, 29 Sep 2021 15:29:26 +0000
Message-ID: <DBAPR08MB581446043DC64B620A92A65098A99@DBAPR08MB5814.eurprd08.prod.outlook.com> (raw)
In-Reply-To: <bed992ff-3bd1-a831-e53e-77120f421ec0@intel.com>

<snip>
> 
> On 9/15/2021 9:33 AM, Ruifeng Wang wrote:
> > Rx descriptor is 16B/32B in size. If the DD bit is set, it indicates
> > that the rest of the descriptor words have valid values. Hence, the
> > word containing DD bit must be read first before reading the rest of
> > the descriptor words.
> >
> > Since the entire descriptor is not read atomically, on relaxed memory
> > ordered systems like Aarch64, read of the word containing DD field
> > could be reordered after read of other words.
> >
> > Read barrier is inserted between read of the word with DD field and
> > read of other words. The barrier ensures that the fetched data is
> > correct.
> >
> > Testpmd single core test showed no performance drop on x86 or N1SDP.
> > On ThunderX2, 22% performance regression was observed.
> >
> 
> Is 22% performance drop value correct? That is a big drop, is it acceptable?
Agree, it is a big drop. Fixing it will require using the barrier less frequently. For ex: read 4 descriptors (4 words containing the DD bits) before using the barrier.

> 
> Is this performance drop valid for all Arm scalar datapath, or is it specific to
> ThunderX2?
This is specific to ThunderX2. N1 CPU does not see any impact. A72 is not tested. Considering that the ThunderXx line of CPUs are not in further development, and it is scalar path, I would not suggest to make further changes to the code.

It would be good to test this on Kunpeng servers and get some feedback.

> 
> > Fixes: 7b0cf70135d1 ("net/i40e: support ARM platform")
> > Cc: stable@dpdk.org
> >
> > Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
> > Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>


  reply	other threads:[~2021-09-29 15:29 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-06  3:31 [dpdk-stable] [PATCH 0/2] i40e Rx descriptor loads ordering Ruifeng Wang
2021-09-06  3:32 ` [dpdk-stable] [PATCH 1/2] net/i40e: fix risk in Rx descriptor read in NEON vector path Ruifeng Wang
2021-09-14 18:33   ` Honnappa Nagarahalli
2021-09-15  8:42     ` Ruifeng Wang
2021-09-06  3:32 ` [dpdk-stable] [PATCH 2/2] net/i40e: fix risk in Rx descriptor read in scalar path Ruifeng Wang
2021-09-14 18:06   ` Honnappa Nagarahalli
2021-09-15  8:33 ` [dpdk-stable] [PATCH v2 0/2] i40e Rx descriptor loads ordering Ruifeng Wang
2021-09-15  8:33   ` [dpdk-stable] [PATCH v2 1/2] net/i40e: fix risk in Rx descriptor read in NEON vector path Ruifeng Wang
2021-09-15  8:33   ` [dpdk-stable] [PATCH v2 2/2] net/i40e: fix risk in Rx descriptor read in scalar path Ruifeng Wang
2021-09-29 15:05     ` Ferruh Yigit
2021-09-29 15:29       ` Honnappa Nagarahalli [this message]
2021-10-11 16:26         ` Ferruh Yigit
2021-10-19 11:14           ` Zhang, Qi Z
2021-11-05  6:57             ` Ruifeng Wang
2021-11-11 10:27               ` Ruifeng Wang
2021-11-11 12:27     ` Zhang, Qi Z
2021-09-24 11:08   ` [dpdk-stable] [PATCH v2 0/2] i40e Rx descriptor loads ordering Zhang, Qi Z

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