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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR08MB4444 Original-Authentication-Results: nvidia.com; dkim=none (message not signed) header.d=none;nvidia.com; dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM5EUR03FT008.eop-EUR03.prod.protection.outlook.com X-MS-Office365-Filtering-Correlation-Id-Prvs: d2054296-5c9a-474e-1505-08d93da39a7b X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: SDwBOtgZUqU/Tr1+6r1uNQ7wqyn/n/9v1dsKm7Xa5AsNjkP/VznUCeOTkjmRYtCaK0lOvU6jS+qXCa4XRLEf3d8L1UceA1WPM+T9Mk+vCoZ/IKBnq7FbJ0c2MsvHkYzGlF+QtE3nu6uNHdKGeM4FRTA0ZvF8xJnubTCXwnHHOT6mrhJACdpAbVlyBg88p6p9QzkiyxQsRVCQQVtB2G1VnbMPrr4pJ9hMqIZWCBpQvz5qdR8tK7xPkUCOBjNjSTnHJ645LPx6zAVWEkRy+SiBButmJWdTeCNxGrryWDdN3tML0Y1uAx5rvg+JOgtGkXIdkFPPcAe5rFtOrnD/ChwpHWKuh+wclE7WvtgtFq5Cug3h5SNtJ9l873TE7L1+VcqnFffRDvpNnDJwo6UX6duTix4sr0WnQCBZKpFKl7VMs7udz2d3hq3viNqMdSsMvGA3FTvhLs+X2KlGYy69srcqZdBb+9QoWA5WT8Ws6V0bA1wFh8ZVjL5EN9UYt9lH4eB0Tj5jVFRwrEiDEmPailSIzO3xicLqziKyWrPPgLPHPjkyyeQ414kRO3HLWRXZhns1JvXIFXRka0Xhgher39KFGeZPElurovnscenV6F2/MyoRkhiaTlmFdNfhKoTNodVFXfw+BrdRt292NsiRPjwIKS5GELoYXRtwgc9+6ZaQnjwysQGOYkQQqLSlx+UgOm/FZvNqRBjhsOfDyuXbG+RFTkjJfZLKY7Yu8xCJ1w9u14Y= X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(4636009)(376002)(396003)(39850400004)(136003)(346002)(46966006)(36840700001)(55016002)(316002)(47076005)(7696005)(8676002)(54906003)(110136005)(36860700001)(2906002)(8936002)(336012)(86362001)(5660300002)(81166007)(82740400003)(52536014)(70586007)(478600001)(70206006)(186003)(26005)(82310400003)(9686003)(356005)(53546011)(450100002)(33656002)(83380400001)(4326008)(6506007)(26123001); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jul 2021 21:52:05.6386 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 863380db-83b7-48b2-58bb-08d93da3a20a X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT008.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR08MB6049 Subject: Re: [dpdk-stable] [PATCH] net/mlx5: remove unwanted barrier X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Hi Slava, Thanks for taking the pain to explain this (this is similar to DD bits in = Intel i40e PMD). Agree, that for ensuring the ordering of the loads between= op_own and the rest of the fields we need a barrier. For Arm architecture,= we can use the barrier for inner sharable domain (rte_smp_rmb()) which is = less costly than the outer sharable domain (rte_io_rmb()). I will re-spin t= his patch. Thanks, Honnappa > -----Original Message----- > From: Slava Ovsiienko > Sent: Thursday, July 1, 2021 7:53 AM > To: Honnappa Nagarahalli ; > dev@dpdk.org; Matan Azrad ; Shahaf Shuler > > Cc: Ruifeng Wang ; Matan Azrad > ; stable@dpdk.org > Subject: RE: [PATCH] net/mlx5: remove unwanted barrier >=20 > Hi, Honnappa >=20 > The rte_io_rmb() was inserted not to prevent the extra access to cqe- > >op_own (the volatile qualifier is quite enough, if we had some doubts, w= e > would insert rte_compiler_barrier), but the real intention of io_rmw was = to > isolate cqe->op_own loads on hardware level. >=20 > cqe points to the Completion Queue Entry (CQE), that is mapped to the > memory that is continuously being updated by the device (NIC). CQE is 64B > size structure and op_own is located at the structure end, and is updated= by > HW in last order, after the entire CQE is completely written to the host > memory. >=20 > After detecting by cqe_check() the CQE is owned by software (hardware > completed operation) the PMD starts touching other CQE fields, i.e. the n= ext > load transactions from CQE are triggered. > And we must make sure these loads happen in correct order, only if cqe- > >op_own load was completed and valid ownership flags were seen, i.e. - do > not allow speculative reads with possible incorrect values fetched). >=20 > Just hypothetical case (I agree in advance - it is very unlikely, but is = not > impossible :)): >=20 > 1. owner =3D cqe->op_own - load A triggered 2. some code is being specula= tively > executed, no barrier 3. length =3D cqe->length - load B triggered 4. Let'= s suppose > CPU reordered A and B, ie order of loads: B, A 5. In memory/CPU cache we > have old CQE, owned by HW 6. B load gets the old length value (invalid) 7= . > Hardware writes the new CQE and CPU cache is invalidated 8. A load gets t= he > CQE is owned by SW and the invalid results of load B will be used by PMD >=20 > Hence, I would consider the patch as risky, and as one that is extremely = hard > to be covered completely with tests - we should test for race conditions = on > multiple architectures, on many CPU models, PCIe root complexes, etc. >=20 > With best regards, > Slava >=20 > > -----Original Message----- > > From: Honnappa Nagarahalli > > Sent: Sunday, June 6, 2021 19:50 > > To: dev@dpdk.org; honnappa.nagarahalli@arm.com; Matan Azrad > > ; Shahaf Shuler ; Slava > > Ovsiienko > > Cc: ruifeng.wang@arm.com; Matan Azrad ; > > stable@dpdk.org > > Subject: [PATCH] net/mlx5: remove unwanted barrier > > > > The IO barrier is not required as cqe->op_own is read once. The checks > > done on the local variable and the memory is not read again. > > > > Fixes: 88c0733535d6 ("net/mlx5: extend Rx completion with error > > handling") > > Cc: matan@mellanox.com > > Cc: stable@dpdk.org > > > > Signed-off-by: Honnappa Nagarahalli > > Reviewed-by: Ruifeng Wang > > --- > > drivers/common/mlx5/mlx5_common.h | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/common/mlx5/mlx5_common.h > > b/drivers/common/mlx5/mlx5_common.h > > index 5028a05b49..a4c29f51f1 100644 > > --- a/drivers/common/mlx5/mlx5_common.h > > +++ b/drivers/common/mlx5/mlx5_common.h > > @@ -195,7 +195,7 @@ check_cqe(volatile struct mlx5_cqe *cqe, const > > uint16_t cqes_n, > > > > if (unlikely((op_owner !=3D (!!(idx))) || (op_code =3D=3D > > MLX5_CQE_INVALID))) > > return MLX5_CQE_STATUS_HW_OWN; > > - rte_io_rmb(); > > + > > if (unlikely(op_code =3D=3D MLX5_CQE_RESP_ERR || > > op_code =3D=3D MLX5_CQE_REQ_ERR)) > > return MLX5_CQE_STATUS_ERR; > > -- > > 2.17.1