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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none x-ms-exchange-crosstenant-authas: Internal x-ms-exchange-crosstenant-authsource: DM4PR11MB5994.namprd11.prod.outlook.com x-ms-exchange-crosstenant-network-message-id: 9f657410-9ea0-406f-8ccc-08da3a0efab6 x-ms-exchange-crosstenant-originalarrivaltime: 20 May 2022 03:15:23.6098 (UTC) x-ms-exchange-crosstenant-fromentityheader: Hosted x-ms-exchange-crosstenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d x-ms-exchange-crosstenant-mailboxtype: HOSTED x-ms-exchange-crosstenant-userprincipalname: m9Q85OasY7yAmRKvJ88lcyWgGXoq0y37nLUM5nuZrBRwnCWFAMdEBkdDJrPKehne6fnL+NB7YpCfgwX1rjO6gw== x-ms-exchange-transport-crosstenantheadersstamped: MW5PR11MB5882 x-originatororg: intel.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org > -----Original Message----- > From: Ke Zhang > Sent: Friday, May 20, 2022 11:00 AM > To: Li, Xiaoyun ; Wu, Jingjing ; > Xing, Beilei ; dev@dpdk.org > Cc: Zhang, Ke1X ; stable@dpdk.org > Subject: [PATCH v2] net/iavf: fix Rx queue interrupt setting > > For Rx-Queue Interrupt Setting, when vf rx interrupt disable(INTENA=3D0),= there > are two ways to write back descriptor to host memory: > > 1)Set WB_ON_ITR bit 0 to Interrupt Dynamic Control Register: > Completed descriptors are posted to host memory according to the internal > descriptor cache policy (in other words when a full cache line is availab= le for > write-back). > > A internal descriptor size is 16 bytes or 32 bytes, a cache line size is = 64 bytes or > 128 bytes from datasheet : > PCIe Global Config 2 - GLPCI_CNF2 (0x000BE004; RO) so the full cache line > could contains 4 packets, it means Network card will send 4 packets to ho= st > when a full cache line is available. > > 2)Set WB_ON_ITR bit 1 to Interrupt Dynamic Control Register: > Completed descriptors also trigger the ITR. Following ITR expiration, all > leftover completed descriptors are posted to host memory. > > Network card will send packet to host even if only one descriptor is comp= leted. > > Changing 1) to 2) to make sure VF send the packet to host even if there i= s only > one rx packet is ready in hardware. > > Fixes: d6bde6b5eae9 ("net/avf: enable Rx interrupt") > Cc: stable@dpdk.org > > Signed-off-by: Ke Zhang Acked-by: Qi Zhang Applied to dpdk-next-net-intel. Thanks Qi