From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 30C4341E1A for ; Wed, 8 Mar 2023 07:30:13 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2A79341143; Wed, 8 Mar 2023 07:30:13 +0100 (CET) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mails.dpdk.org (Postfix) with ESMTP id 76A5340E03; Wed, 8 Mar 2023 07:30:09 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678257010; x=1709793010; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=QKFZzUrG5s5o12wWNt0oNoOHKZgCGsAfUB+eyjRJtPc=; b=IQecpxtWfgy0jq7J7EVcTwFABJGgLj0KYZEctULeIpP0FuxUw6PUdP1N cHV9T6aRoje0Aj27KSkRGlbb4wnlHSws+e5cb4MR0dqK1fC5Yf4NX//cQ tg6exdwSv0lLQc+XyApC74OKv02AmMLK1wTwcS/HduVev+3sirk7PYpNk or3h080oRaSqHXEuie2CKV3XkBmRMJUk8gFGW+wJ9LbiI6tinUdhmXdCW 55WeTrhdTTezeYKIqY6PTBXVaar4HoyFLr7lAKcRBwcevJdP2CJsPjf2/ T9P7cVkLHcVsyx54oCP1qlim16kBU2xHap77mgpZJUtFvKYmTQAXE4xxr A==; X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="319904988" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="319904988" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2023 22:30:08 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="922663986" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="922663986" Received: from fmsmsx602.amr.corp.intel.com ([10.18.126.82]) by fmsmga006.fm.intel.com with ESMTP; 07 Mar 2023 22:30:08 -0800 Received: from fmsmsx610.amr.corp.intel.com (10.18.126.90) by fmsmsx602.amr.corp.intel.com (10.18.126.82) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Tue, 7 Mar 2023 22:30:07 -0800 Received: from fmsedg602.ED.cps.intel.com (10.1.192.136) by fmsmsx610.amr.corp.intel.com (10.18.126.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21 via Frontend Transport; Tue, 7 Mar 2023 22:30:07 -0800 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (104.47.70.106) by edgegateway.intel.com (192.55.55.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.21; Tue, 7 Mar 2023 22:30:07 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=bbjpwAPT6nrqJzWxlNXd0ont86K6RSXYHnoPbXtZ0kpdTbxCA62bdxh9+DXzY0xWScspxwV01FFnpeUaUI1cNhg1iKFS1mntl1NRxU2g1/UTM+vtW+RtM80glq3FeIBt+e6OAvdf3k5+CdWHGENRRvxnZgNu6459thNF8y9xogIrb3DdllhjUvbdlczPJiOteStKmNa7EUKerGl45tsdVYRXlaoT3D47qEgyP+e6DITlK8HTI5oBHhMYTkOksBD202+UFgPppKGvYm3t6jxlGdymnFyLrgJXQfRQ2QaQLt6tdE4R3R9cttcKoTj57KtORHrotrSKRwtttAyJICEdgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=x9kKE+zp4shUxad4w+f/ueb5IstRvsgpLUuXDEKVrcU=; b=lfJ36brOQPK24bxAGikYZu24REYSOwRCC0whcQ9wD1w+lKribcN5oyB/4F9NyPUuWJb2GcAcurk3hfsO1ikV6tbs7XPR6h65JqcNzgWGuPmVE8lkkbUIPyXTdJjlgq6dNAeSpHVg/txY36CLEVv+5gI0BFnla9s3jmiSv8UXK2CNi04xtZMBdBB/lJzA8R5tav47fa4NAFaN3jx6DWzWGanUszJ3EU5q9D6iG4X3sgPlWyx0cZC+qTScNVr5fCxqnwlIItF3t+iKguhigi7MZq2j2eeappCtT9KH4sB6OAocbiJjskYMDfiOz4orocQezngK7zHVrkJbpcswO/Pwww== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Received: from DM4PR11MB5994.namprd11.prod.outlook.com (2603:10b6:8:5d::20) by DS7PR11MB6296.namprd11.prod.outlook.com (2603:10b6:8:94::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6156.28; Wed, 8 Mar 2023 06:30:00 +0000 Received: from DM4PR11MB5994.namprd11.prod.outlook.com ([fe80::2c5d:49cd:a9b4:f764]) by DM4PR11MB5994.namprd11.prod.outlook.com ([fe80::2c5d:49cd:a9b4:f764%7]) with mapi id 15.20.6178.017; Wed, 8 Mar 2023 06:30:00 +0000 From: "Zhang, Qi Z" To: "Wu, Wenjun1" , "Su, Simei" , "Yang, Qiming" CC: "dev@dpdk.org" , "stable@dpdk.org" Subject: RE: [PATCH v2] net/ice: fix incorrect Rx timestamp Thread-Topic: [PATCH v2] net/ice: fix incorrect Rx timestamp Thread-Index: AQHZUXfN5irbd+3imk2AoZCV086UX67wY5IAgAAIPsA= Date: Wed, 8 Mar 2023 06:30:00 +0000 Message-ID: References: <20230302134501.201032-1-simei.su@intel.com> <20230308043655.324241-1-simei.su@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: DM4PR11MB5994:EE_|DS7PR11MB6296:EE_ x-ms-office365-filtering-correlation-id: 4d104273-8a44-41fe-052d-08db1f9e8b11 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: p5cqg8kSwv2K4xJJHL8J/9J7LfiZQ7pIeJ0KAvWeL5LD37LR54RhfXriB0+7zUX+Lf3DhXzkhEKo3IQnpo8bgNLo1qtA5dkQnZqAmcIC47q+UFrhP931TI22fuZycCjFZCVZeqtp4QO1iyPBPNte52whWAmtFDjsLVAjThDBrwwG+TrSb1pYd+p4VCMqI1kkhuh2hbTsMLdp3njpRIRRlMQDOVd2+PtEzjle2Q9HJ2Rt7wGky1fqQVTCkK3CTSgvmsEdJ7PggFPjeU7mZ2JW1k7aYJ3gcMuh+I/nb4NGVlKpZhwgPOzDCGjJBuHowlx6k0VD7tvOdCG734a9UzZuJ54BDKKfkItYT33rTf7LWeQEslzTp3V08wkInYnjsw+XRYcbpapW2CTABp79HWk5fEWP8WvJa65ANgEFVrBcwHDsME66yFLi1sLFTiF68c/JgP4nKdXozknf2ld/4XpD6E+nnJhi2LHngTQ9AA4/RaWD241PcltT5Tmwf5jsZg5DwgIEdxUsgOgH7J7+6rNii+nfh2H9tpyq2a34zfu2cwiXYlTuhY0fXdEZZPj/BDjJ2vd05YNZPA8PA+DzJ+qV2mtI4f96JXbcQhGHgcjW1YrdSaLBUwMY4VkM+wG9b4vYPpi7b1el0mEOOjx+kvpS3y2gFigmSTvahhc7PDvm1j9JSFqrAHgoshFODOI9YnAXTVA9WtKEyTH/MG5LVF2i+A== x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DM4PR11MB5994.namprd11.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230025)(346002)(376002)(136003)(39860400002)(396003)(366004)(451199018)(55016003)(450100002)(6636002)(478600001)(54906003)(110136005)(83380400001)(316002)(33656002)(82960400001)(122000001)(38100700002)(8676002)(76116006)(64756008)(66446008)(4326008)(186003)(9686003)(6506007)(53546011)(52536014)(7696005)(71200400001)(26005)(66556008)(66946007)(8936002)(86362001)(66476007)(2906002)(38070700005)(41300700001)(5660300002); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?7PpVffNDkDm0W3RH5Kgh9y3BUALHL/u8+NzQfybFSr60KsrHBZCoGaoc+r9E?= =?us-ascii?Q?olDxbDMELGG26V9IX5hyrdr1HHpaSLj/JPighCwCgAaNUt/OPHOSjVG2byki?= =?us-ascii?Q?P0iFiCGTphXjnVQdrQ4+QiBS34X3AqL0Ipot1DSr5GTIbSbTbJyHA0N0I6s2?= =?us-ascii?Q?dYgnw31I1tDCJjIYs9YNoMd1wqdmOvYjhYvvslTF5jM5un504ooIh4sD9q5p?= =?us-ascii?Q?OqoyA2B++2IGBF2dvceTCuj5b77uxy9XlapKS0oO6pbGqDs7jXbRTUNwAyu6?= =?us-ascii?Q?umf4AdSZsD4xHTr/CM48XNooHavfXt5r8d3Y+DQ+bqckZnGj08hrdSTc9XoV?= =?us-ascii?Q?l46pUifLhu3jA1f6ShjdLPOMLaGn0SNhOBnntdjUAFfHBJlcha2KIw04Vz4e?= =?us-ascii?Q?SDUkZO9Wv3OTEXCx+e12cpTKLIwiZEglBAqjV5AUTLM2x4I/AHbdcQ8+5EGA?= =?us-ascii?Q?4qR7XZnRfYMqdTxzosZLl885XWSAcBAE0IKN55CJrOnETvgzWbpXiFlCxGwh?= =?us-ascii?Q?8K+B68vjGaw7C0+eO5pfbk/OKTASz5TIGIpeXiPyxV50PP5lJSPjOKBgAaRL?= =?us-ascii?Q?aXhFL86CcXhaJqef1KxFtwpa6Vr9ne/J+kYVdKGsxC5ClZt5emVPS7PCauRw?= =?us-ascii?Q?2cnVQVjk0QjERnENs8QsFoZKfdqFt/NYrSTnwuDabFX4+pEIa8ALs3tBnr+7?= =?us-ascii?Q?i4BZXjyOfqg23lFCJjQgY7ishkdudVm8A+Khi7P+ofUXoFuIzLe5nGnvuEH3?= =?us-ascii?Q?Y/c1zPM1reGvV/CoggzMgAikos6zgEFggr31aufVRY5JtNC49WLO9cOzJT+p?= =?us-ascii?Q?GkLJhbYeX5BzzewLseGqeM+hkckjPEjYKiKTEsTdzwx9UPRt4AsQnGXF58xY?= =?us-ascii?Q?7DXtWMSMHivTtBoWBjdAGdbMIIIv4u7CwAeYj2o0svp2P8xKxN1DqHGvn25H?= =?us-ascii?Q?bqoenO10TyyBERpdpx/B4uLGYNOr1uiU4+ZBIIdY7yy0R6j1b6+lzfSx5cr/?= =?us-ascii?Q?rd3E8qqpOgBKFX5bRDhPtJcX75zMPZeBR5PdEt+UDBP8x9JBgkCfqDwpdWWN?= =?us-ascii?Q?mW9tcETHxPxYRNlARgLJ+Qv1AOqkJByrK2v4tGd3p6AVjC97k9eI+z80q8N4?= =?us-ascii?Q?tEugaDeMUYVdU0OtMaJShYiTD9/UDDl7f29dQ3jnsoOU/rMivIvujDQ4/Ffp?= =?us-ascii?Q?mma27rldzUa5/5pbWyl229B4TkN9bHeGxJNUNQHpBk8utitSqeKIGI6g/TZo?= =?us-ascii?Q?eJv+BbYPYG9R2O8N/Nfq4Qm/T0S28JCymhpFGoemhLh6xS48ghHhTAVzYM0a?= =?us-ascii?Q?pGIZra3RENUY6zD5AyfjbzKAf2tUHQMGEMn+w7UPSeu2AKf3GcdffJG4y/Fs?= =?us-ascii?Q?ks3dHKWEm7THzmx9QxsogdJdgic4lV+Yf+IX5vNWnJrRwtPv43OWd9EY9jk1?= =?us-ascii?Q?GfiniSNMg9Ty0kbwdNMIFDyjsENjttC0Kg3c4xoRbRtBkRC2eV3pBcGBjS5/?= =?us-ascii?Q?xoBmdxwnoFoGXamlupY2uzzaCC7dcGjDc/7LOxHMCvKroFNRwI6xfLviIaHz?= =?us-ascii?Q?ZFh8P92N7WcwB0a6gUeNYYrWrnIcFgc/OXtwKIB3?= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM4PR11MB5994.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4d104273-8a44-41fe-052d-08db1f9e8b11 X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Mar 2023 06:30:00.1343 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: pRZrjkNrn/o9wgIwblLsP0MASScSDyCndVOWvfWwtv4D1YsiM3MkgGKTknJfd2od4qK4uc9hVQS9M6VW7H8PGA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR11MB6296 X-OriginatorOrg: intel.com X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org > -----Original Message----- > From: Wu, Wenjun1 > Sent: Wednesday, March 8, 2023 2:00 PM > To: Su, Simei ; Zhang, Qi Z ; > Yang, Qiming > Cc: dev@dpdk.org; stable@dpdk.org > Subject: RE: [PATCH v2] net/ice: fix incorrect Rx timestamp >=20 >=20 >=20 > > -----Original Message----- > > From: Su, Simei > > Sent: Wednesday, March 8, 2023 12:37 PM > > To: Zhang, Qi Z ; Yang, Qiming > > > > Cc: dev@dpdk.org; Wu, Wenjun1 ; Su, Simei > > ; stable@dpdk.org > > Subject: [PATCH v2] net/ice: fix incorrect Rx timestamp > > > > For E822, the time value in Rx Flex Descriptors is 0 due to the > > missing PHY clock timer setup. Also, the source clock index in use is > > based on device capabilities instead of always being zero. > > > > Fixes: 953e74e6b73a ("net/ice: enable Rx timestamp on flex > > descriptor") > > Fixes: 646dcbe6c701 ("net/ice: support IEEE 1588 PTP") > > Fixes: fb800fde66f4 ("net/ice/base: work around missing PTP > > capabilities") > > Cc: stable@dpdk.org > > > > Signed-off-by: Simei Su > > --- > > v2: > > * Refine commit title and commit log. > > * Remove duplicate code. > > * Rework share code for "SIMICS_SUPPORT". > > > > drivers/net/ice/base/ice_common.c | 4 +--- > > drivers/net/ice/ice_ethdev.c | 36 ++++++++++++++++++++++---------= ----- > > drivers/net/ice/ice_rxtx.h | 11 ++++++----- > > 3 files changed, 29 insertions(+), 22 deletions(-) > > > > diff --git a/drivers/net/ice/base/ice_common.c > > b/drivers/net/ice/base/ice_common.c > > index 5391bd6..1a02aad 100644 > > --- a/drivers/net/ice/base/ice_common.c > > +++ b/drivers/net/ice/base/ice_common.c > > @@ -2554,9 +2554,7 @@ ice_parse_1588_func_caps(struct ice_hw *hw, > > struct ice_hw_func_caps *func_p, > > struct ice_aqc_list_caps_elem *cap) { > > struct ice_ts_func_info *info =3D &func_p->ts_func_info; > > - u32 number =3D ICE_TS_FUNC_ENA_M | ICE_TS_SRC_TMR_OWND_M | > > - ICE_TS_TMR_ENA_M | ICE_TS_TMR_IDX_OWND_M | > > - ICE_TS_TMR_IDX_ASSOC_M; > > + u32 number =3D LE32_TO_CPU(cap->number); > > u8 clk_freq; > > > > ice_debug(hw, ICE_DBG_INIT, "1588 func caps: raw value %x\n", > > number); diff --git a/drivers/net/ice/ice_ethdev.c > > b/drivers/net/ice/ice_ethdev.c index 0d011bb..9a88cf9 100644 > > --- a/drivers/net/ice/ice_ethdev.c > > +++ b/drivers/net/ice/ice_ethdev.c > > @@ -2413,6 +2413,17 @@ ice_dev_init(struct rte_eth_dev *dev) > > /* Initialize TM configuration */ > > ice_tm_conf_init(dev); > > > > + if (ice_is_e810(hw)) > > + hw->phy_cfg =3D ICE_PHY_E810; > > + else > > + hw->phy_cfg =3D ICE_PHY_E822; > > + > > + if (hw->phy_cfg =3D=3D ICE_PHY_E822) { > > + ret =3D ice_start_phy_timer_e822(hw, hw->pf_id, true); > > + if (ret) > > + PMD_INIT_LOG(ERR, "Failed to start phy timer\n"); > > + } > > + > > if (!ad->is_safe_mode) { > > ret =3D ice_flow_init(ad); > > if (ret) { > > @@ -5814,11 +5825,6 @@ ice_timesync_enable(struct rte_eth_dev *dev) > > return -1; > > } > > > > - if (ice_is_e810(hw)) > > - hw->phy_cfg =3D ICE_PHY_E810; > > - else > > - hw->phy_cfg =3D ICE_PHY_E822; > > - > > if (hw->func_caps.ts_func_info.src_tmr_owned) { > > ret =3D ice_ptp_init_phc(hw); > > if (ret) { > > @@ -5939,16 +5945,17 @@ ice_timesync_read_time(struct rte_eth_dev > > *dev, struct timespec *ts) > > struct ice_hw *hw =3D ICE_DEV_PRIVATE_TO_HW(dev->data- > > >dev_private); > > struct ice_adapter *ad =3D > > ICE_DEV_PRIVATE_TO_ADAPTER(dev->data- > > >dev_private); > > + uint8_t tmr_idx =3D hw->func_caps.ts_func_info.tmr_index_assoc; > > uint32_t hi, lo, lo2; > > uint64_t time, ns; > > > > - lo =3D ICE_READ_REG(hw, GLTSYN_TIME_L(0)); > > - hi =3D ICE_READ_REG(hw, GLTSYN_TIME_H(0)); > > - lo2 =3D ICE_READ_REG(hw, GLTSYN_TIME_L(0)); > > + lo =3D ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); > > + hi =3D ICE_READ_REG(hw, GLTSYN_TIME_H(tmr_idx)); > > + lo2 =3D ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); > > > > if (lo2 < lo) { > > - lo =3D ICE_READ_REG(hw, GLTSYN_TIME_L(0)); > > - hi =3D ICE_READ_REG(hw, GLTSYN_TIME_H(0)); > > + lo =3D ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); > > + hi =3D ICE_READ_REG(hw, GLTSYN_TIME_H(tmr_idx)); > > } > > > > time =3D ((uint64_t)hi << 32) | lo; > > @@ -5964,6 +5971,7 @@ ice_timesync_disable(struct rte_eth_dev *dev) > > struct ice_hw *hw =3D ICE_DEV_PRIVATE_TO_HW(dev->data- > > >dev_private); > > struct ice_adapter *ad =3D > > ICE_DEV_PRIVATE_TO_ADAPTER(dev->data- > > >dev_private); > > + uint8_t tmr_idx =3D hw->func_caps.ts_func_info.tmr_index_assoc; > > uint64_t val; > > uint8_t lport; > > > > @@ -5971,12 +5979,12 @@ ice_timesync_disable(struct rte_eth_dev *dev) > > > > ice_clear_phy_tstamp(hw, lport, 0); > > > > - val =3D ICE_READ_REG(hw, GLTSYN_ENA(0)); > > + val =3D ICE_READ_REG(hw, GLTSYN_ENA(tmr_idx)); > > val &=3D ~GLTSYN_ENA_TSYN_ENA_M; > > - ICE_WRITE_REG(hw, GLTSYN_ENA(0), val); > > + ICE_WRITE_REG(hw, GLTSYN_ENA(tmr_idx), val); > > > > - ICE_WRITE_REG(hw, GLTSYN_INCVAL_L(0), 0); > > - ICE_WRITE_REG(hw, GLTSYN_INCVAL_H(0), 0); > > + ICE_WRITE_REG(hw, GLTSYN_INCVAL_L(tmr_idx), 0); > > + ICE_WRITE_REG(hw, GLTSYN_INCVAL_H(tmr_idx), 0); > > > > ad->ptp_ena =3D 0; > > > > diff --git a/drivers/net/ice/ice_rxtx.h b/drivers/net/ice/ice_rxtx.h > > index 4947d5c..94f6bcf 100644 > > --- a/drivers/net/ice/ice_rxtx.h > > +++ b/drivers/net/ice/ice_rxtx.h > > @@ -349,26 +349,27 @@ static inline > > uint64_t ice_tstamp_convert_32b_64b(struct ice_hw *hw, struct > > ice_adapter *ad, > > uint32_t flag, uint32_t in_timestamp) { > > + uint8_t tmr_idx =3D hw->func_caps.ts_func_info.tmr_index_assoc; > > const uint64_t mask =3D 0xFFFFFFFF; > > uint32_t hi, lo, lo2, delta; > > uint64_t ns; > > > > if (flag) { > > - lo =3D ICE_READ_REG(hw, GLTSYN_TIME_L(0)); > > - hi =3D ICE_READ_REG(hw, GLTSYN_TIME_H(0)); > > + lo =3D ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); > > + hi =3D ICE_READ_REG(hw, GLTSYN_TIME_H(tmr_idx)); > > > > /* > > * On typical system, the delta between lo and lo2 is ~1000ns, > > * so 10000 seems a large-enough but not overly-big guard > band. > > */ > > if (lo > (UINT32_MAX - > > ICE_TIMESYNC_REG_WRAP_GUARD_BAND)) > > - lo2 =3D ICE_READ_REG(hw, GLTSYN_TIME_L(0)); > > + lo2 =3D ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); > > else > > lo2 =3D lo; > > > > if (lo2 < lo) { > > - lo =3D ICE_READ_REG(hw, GLTSYN_TIME_L(0)); > > - hi =3D ICE_READ_REG(hw, GLTSYN_TIME_H(0)); > > + lo =3D ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); > > + hi =3D ICE_READ_REG(hw, GLTSYN_TIME_H(tmr_idx)); > > } > > > > ad->time_hw =3D ((uint64_t)hi << 32) | lo; > > -- > > 2.9.5 >=20 > Acked-by: Wenjun Wu Applied to dpdk-next-net-intel. Thanks Qi >=20 > Regards, > Wenjun