From mboxrd@z Thu Jan 1 00:00:00 1970
Return-Path: <stable-bounces@dpdk.org>
Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124])
by inbox.dpdk.org (Postfix) with ESMTP id 1CA3AA0C4C
for <public@inbox.dpdk.org>; Tue, 23 Nov 2021 21:41:48 +0100 (CET)
Received: from [217.70.189.124] (localhost [127.0.0.1])
by mails.dpdk.org (Postfix) with ESMTP id 069A241170;
Tue, 23 Nov 2021 21:41:48 +0100 (CET)
Received: from NAM12-BN8-obe.outbound.protection.outlook.com
(mail-bn8nam12on2080.outbound.protection.outlook.com [40.107.237.80])
by mails.dpdk.org (Postfix) with ESMTP id 548AD4003C;
Tue, 23 Nov 2021 21:41:45 +0100 (CET)
ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;
b=e4j40nRfxQcuducUpqgznTY/arWZVyvgI3IgXf+kXR1VHXyD118Buu41qkjYeS+GiL1u7ZYVGNYG85PhjLawgPYjOqU7arsW1shvoYYVB96Wa0/ozx7TujU4AWjI4HcC0s35yV38xCcVNnpiOqVpfRekmnp5bg9vS4W2RimXvpcocou3k3d6GAUNuGlT/4hL0V120b3wY+NZo1UsXGtjr1O1Ld4l/+weMnwZMIde+STS5WA5WfVsHCHUeWbdzfdEqifATANK4JH67kmwD/ExrZtka1x3/ih/2X+Zj6GNM+ULI5IHcsoDb5NmJjRMU58bLyOrOgObjydMzbBKkr+Pow==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;
s=arcselector9901;
h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;
bh=2gPdWmUjY5CgQhFmwqaFlKGoTrhJrIxmz9tmkbrchhs=;
b=KYHnmBSdOTXwzjOqFLaA+k1O3EQ7JShEIvys31aHOuxBPzFi0CWVAIovzLECzhpp8L0jT92Skegp41QJtvi3jlOco3DIC6Gm2DHiGFXPfzBAJQZOPyXOjBQfVMWa7ayH+Punn2R6hEL3WILVbQPrTzdgS4pTd06CLN1h59Nzu0eyKw7Uh0vXrJxK+R+SLDdq503GB5KSWOVcy19pM6+nXCLLGpLtWIgrvDHPenqlRf7FWvVh56tHLfVYilAKLcFQ7+RUH7wg0RJRvkPac/r4edYqCaKayTYla2prh8M3ddh/NKTqqE+9Zp91bI2zW8ue2HPcfsE5VIqlmOBEbudpQQ==
ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass
smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com;
dkim=pass header.d=nvidia.com; arc=none
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;
s=selector2;
h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;
bh=2gPdWmUjY5CgQhFmwqaFlKGoTrhJrIxmz9tmkbrchhs=;
b=KeLPawTlblBIbBGkZlmMP6ZCtzTUIrqSCAvGVOHw8WURiQODb4pseJAii2qxW7OUTor4hZJUbANib454vjmpMYf944+eulYe3qXK+ZohmCMt4QOreenZIrZNxtHu7QX66OSBJ5z4MkJ7xxTimx+tQAXPW3zC6dLtkpo4PnevGMbSMuNPEkyWA0q2rgSvZxfBxdA9VDQmcr+A1x4uuNfYZah5D8ZV1xJenhQhM3lEKIgBYeuhZ3L4rJTMmwI/tOXsEY6kf2F/cl0Uqq71AUtHLNEYgfe3xclcgM9ZXlR6sgxigvNVFUjAyhB927Du/FkZo59HMgFNomfAv/mPCoXHqQ==
Received: from DM4PR12MB5312.namprd12.prod.outlook.com (2603:10b6:5:39d::20)
by DM4PR12MB5359.namprd12.prod.outlook.com (2603:10b6:5:39e::24) with
Microsoft SMTP Server (version=TLS1_2,
cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.22; Tue, 23 Nov
2021 20:41:43 +0000
Received: from DM4PR12MB5312.namprd12.prod.outlook.com
([fe80::7cf5:9d34:fc6b:b4a4]) by DM4PR12MB5312.namprd12.prod.outlook.com
([fe80::7cf5:9d34:fc6b:b4a4%9]) with mapi id 15.20.4713.019; Tue, 23 Nov 2021
20:41:43 +0000
From: Raslan Darawsheh <rasland@nvidia.com>
To: Michael Baum <michaelba@nvidia.com>, "dev@dpdk.org" <dev@dpdk.org>
CC: Matan Azrad <matan@nvidia.com>, Slava Ovsiienko <viacheslavo@nvidia.com>,
"stable@dpdk.org" <stable@dpdk.org>
Subject: RE: [PATCH 3/3] net/mlx5: fix missing adjustment MPRQ stride devargs
Thread-Topic: [PATCH 3/3] net/mlx5: fix missing adjustment MPRQ stride devargs
Thread-Index: AQHX4JlXNJFtEzG9hUmZvdocFIcn/KwRk3QA
Date: Tue, 23 Nov 2021 20:41:43 +0000
Message-ID: <DM4PR12MB53128AA3ED60431FA8690F5CCF609@DM4PR12MB5312.namprd12.prod.outlook.com>
References: <20211123183805.2905792-1-michaelba@nvidia.com>
<20211123183805.2905792-4-michaelba@nvidia.com>
In-Reply-To: <20211123183805.2905792-4-michaelba@nvidia.com>
Accept-Language: en-US
Content-Language: en-US
X-MS-Has-Attach:
X-MS-TNEF-Correlator:
authentication-results: dkim=none (message not signed)
header.d=none;dmarc=none action=none header.from=nvidia.com;
x-ms-publictraffictype: Email
x-ms-office365-filtering-correlation-id: 23a214cc-3b9e-4eb6-c604-08d9aec1a90f
x-ms-traffictypediagnostic: DM4PR12MB5359:
x-microsoft-antispam-prvs: <DM4PR12MB5359EA17B6889CD99A3988B6CF609@DM4PR12MB5359.namprd12.prod.outlook.com>
x-ms-oob-tlc-oobclassifiers: OLM:6108;
x-ms-exchange-senderadcheck: 1
x-ms-exchange-antispam-relay: 0
x-microsoft-antispam: BCL:0;
x-microsoft-antispam-message-info: YdTkDZwc/QbrSXcpeFtgYEuep6UxiEJ4bK1/YP5P0fwgVfgDJAl6x/7/+GwMo+buxiXAlLeV7EVcfrPpm5HQcMryTD/1W7rYWVO5GMLt2u+3ikVWy3v0E+vlj/u2h9cSyXqDj0QCGyML4aCIOmbZ+PNgJxlbnTrSs0lAVmsSFa22VKZMaY63p5CDlharmHKPOZj8E1V7wQEenJ8vBxObxySQ71d+ZaR8Z0J9C2rm40CoZFiRNrwVP0QoI4ukJ4o1sOUZLi90CjcPlFiHc3LkOs4lILeCS9EJ/PmDlx5LOeVRT/yinFHJRZLeY1vMJQmuKkPI4BaXeRM2eXW/1Wbq4aY9P45y3DIxZm4hiCNjZqs0ACNeDT/OqvefagxO3Bn9Ne/yajaBkzqBiR9YaKAYL2tpySZYDdZwrSiSwscurbsB4svsVdSiViNGeHfDUALTS42TWyLLsi7Ntd/uOl3lh8FF3xgD9FXjU1JZLLIvMepUrPpflPMTRZebD09SvaNeT9k3GXOREIX3FkUmWxkG7uUXhbm2i9BdXmrqYw+3Ye17gyLh+QVTWL49jn64eCBo74D3jXOeD9CdEcby7upctPd404eOhwFgscxqkTjqjGpd6BcoVRvcNZmbW+CQhhuMsynDB+sCay/P/umDqHM5KubFxJFo7EJ8DRL+TrDumsISuIEbwWrnEy5thxO8rjey1x8QDt8Y3tdrLQ1GHkPX1g==
x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:;
IPV:NLI; SFV:NSPM; H:DM4PR12MB5312.namprd12.prod.outlook.com; PTR:; CAT:NONE;
SFS:(4636009)(366004)(2906002)(8676002)(450100002)(186003)(86362001)(66556008)(110136005)(4326008)(9686003)(316002)(54906003)(66476007)(66446008)(64756008)(71200400001)(122000001)(53546011)(83380400001)(508600001)(33656002)(38100700002)(8936002)(52536014)(6506007)(5660300002)(55016003)(7696005)(76116006)(38070700005)(26005)(66946007);
DIR:OUT; SFP:1101;
x-ms-exchange-antispam-messagedata-chunkcount: 1
x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?t8LOZtDReGBsYQcUKcoIZGA7TLkldYjxgiS+/fLbyDgfp2CUwqC2ewDe9qSt?=
=?us-ascii?Q?HCNzvQ63e+lY4Ml/vRMbFFBM65z1lwuGK4dznt7Id8CjMwZLO/SENdIs8NwO?=
=?us-ascii?Q?Cukk6TLjtFFfZYCN+2R5yybYVGrkG/ZM2ab4ZfOE9b2WvCN342/x2KIyW0FN?=
=?us-ascii?Q?6fHYLVuiKBVhBtZJOUcUzkPmQkmciMKJZYnUN9cmkJlVcaT7GUfs+8BpP+wI?=
=?us-ascii?Q?ZN6AwqSSzwXJMnnV3e/29BILP9GKzCgA9lGU+uvL8plW9EYTL9K5LFJtTh0+?=
=?us-ascii?Q?OE04arHasT6yXy7PlEEYIPX8MSZlUjT3rspytG7QG8wVNvxknf4xwO0VGcx+?=
=?us-ascii?Q?8Balck9iSBTnxtBpciD6ofjapBi+D1EVyxvCucABBSoWELSEEjmgrvTPPx4w?=
=?us-ascii?Q?dUobTFA0GMMpxjg7zmSGE2P7ke3y1maAaGjkudsECyzvNWTHhjMrHFW0Zoxk?=
=?us-ascii?Q?+1DK7C4wYImj6Cbu3jDm6G48LgPnRfU3PFi9/CY3+Ql3I8YmPoO6f1p3TBfb?=
=?us-ascii?Q?Dr7AWYO8K6VciLgder9vDHgUMyPX2umgprNYAko4Y7bH3ztOdqF4hM1OA5g0?=
=?us-ascii?Q?zUWnSEQfXtx+X3iGNzXmFRRG2mueJ9wG9J/rDC0pYgofVqHwDO0JMqa7amj/?=
=?us-ascii?Q?+9fp6GO6sXk1gUKDZQbqDUnsyMVTEMLbGUotrjfFCfUb74ycMhzV3kl9YtHi?=
=?us-ascii?Q?vnYjnCfgCwcEojkqT0r3JTWOGxhrHuK46xMIkP2btcF/dXcHLBnDHP/8mNAK?=
=?us-ascii?Q?1pUv4nqG9Rzme7vbZc2EuWF9AS0g/lnpscCZ68dlRHrrcYOvwxkOSE3ArR0W?=
=?us-ascii?Q?nuQGWZF8HXgI3AtMgvZCsg8iUqFI8e0FfplFanMFb3kh1vWd0nhgXFOk+xPo?=
=?us-ascii?Q?am2I6jfXb+HJOTf8Gt9lYAIqHXPdGjgNRwXnXYYoHGgSS5LhlHpDqBKUY5M3?=
=?us-ascii?Q?v5IuMeoatgV9c9Ee+CyTglmN8WAFgcH0gTB0dAvwcD7Byhk9KrDQqlpVQQ16?=
=?us-ascii?Q?1Mnpkrj0AgZXR0bZ1cKtortLm0b6TlyZQRdc5Oh/LPbmYFhu9ai0+O6Vbyq0?=
=?us-ascii?Q?EIF19FHeINL7he8Dl1k8qk5a3ILF1gnI0e6kNhSUOzFEn1emOaaEdSTjbWRW?=
=?us-ascii?Q?V/Lz1MDCDyTVpw26TJuUK7uq3Qlq0VDJ7FiCVxYqQ2Tu4Bn1WI5DZAbo3qTd?=
=?us-ascii?Q?IYYrHGBaHbfKDY6lihZTgk2YaZq8UyHxtAekJ3bh+VGxzju39h+SJkDEq9Il?=
=?us-ascii?Q?xnyQFkDwrX+HVOjB2N8dni8n8A5D4kXdUseQ+GOAEypTVbvPhpglQ8PnR7J9?=
=?us-ascii?Q?HwmNf+9gORoVhQfX2EmWPGVs8vE3EM+ziUVAMis5raoTX4/5soYfzp2xAzqN?=
=?us-ascii?Q?pqxjZEtgfwp7LokiPtF6Xnbiaa98if4qi6gy+3A8MmrEhP2xdChQpIGCZ2ck?=
=?us-ascii?Q?IMVFZS0O7qLvhCudre8xkdsS9pmBPySnEYrE/SwiW2L0nezJPK5kHpgGqDUz?=
=?us-ascii?Q?qkjTODn4nxTHrLIe6FseZ0EJjnu+JTphF2vGnQo+/PJ60P/74BVUNmomThQ8?=
=?us-ascii?Q?gEy2lB2iqhanbBMd8/7COuU0WWNp5SsN5oniTcb4iJjMfTM9il7Hp+4P+r8q?=
=?us-ascii?Q?qq6cpjHp/cv12ShW0Q8naio=3D?=
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
MIME-Version: 1.0
X-OriginatorOrg: Nvidia.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-AuthSource: DM4PR12MB5312.namprd12.prod.outlook.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 23a214cc-3b9e-4eb6-c604-08d9aec1a90f
X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Nov 2021 20:41:43.6626 (UTC)
X-MS-Exchange-CrossTenant-fromentityheader: Hosted
X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a
X-MS-Exchange-CrossTenant-mailboxtype: HOSTED
X-MS-Exchange-CrossTenant-userprincipalname: W2dLm0PddaGxjvA247BBAnMOX3VQFOHf4BTLFEF06P5TY4Nprj7FwJ1p/CWZZCJC2VJiGwu+OMdZfFKl/UHIEQ==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5359
X-BeenThere: stable@dpdk.org
X-Mailman-Version: 2.1.29
Precedence: list
List-Id: patches for DPDK stable branches <stable.dpdk.org>
List-Unsubscribe: <https://mails.dpdk.org/options/stable>,
<mailto:stable-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://mails.dpdk.org/archives/stable/>
List-Post: <mailto:stable@dpdk.org>
List-Help: <mailto:stable-request@dpdk.org?subject=help>
List-Subscribe: <https://mails.dpdk.org/listinfo/stable>,
<mailto:stable-request@dpdk.org?subject=subscribe>
Errors-To: stable-bounces@dpdk.org
Hi,
> -----Original Message-----
> From: Michael Baum <michaelba@nvidia.com>
> Sent: Tuesday, November 23, 2021 8:38 PM
> To: dev@dpdk.org
> Cc: Matan Azrad <matan@nvidia.com>; Raslan Darawsheh
> <rasland@nvidia.com>; Slava Ovsiienko <viacheslavo@nvidia.com>; Michael
> Baum <michaelba@nvidia.com>; stable@dpdk.org
> Subject: [PATCH 3/3] net/mlx5: fix missing adjustment MPRQ stride devargs
>=20
> From: Michael Baum <michaelba@nvidia.com>
>=20
> In Multy-Packet RQ creation, the user can choose the number of strides an=
d
> their size in bytes. The user updates it using specific devargs for both =
of
> these parameters.
> The above two parameters determine the size of the WQE which is actually
> their product of multiplication.
>=20
> If the user selects values that are not in the supported range, the PMD
> changes them to default values. However, apart from the range limitations
> for each parameter individually there is also a minimum value on their
> multiplication. When the user selects values that their multiplication ar=
e
> lower than minimum value, no adjustment is made and the creation of the
> WQE fails.
>=20
> This patch adds an adjustment in these cases as well. When the user selec=
ts
> values whose multiplication is lower than the minimum, they are replaced
> with the default values.
>=20
> Fixes: ecb160456aed ("net/mlx5: add device parameter for MPRQ stride
> size")
> Cc: stable@dpdk.org
>=20
> Signed-off-by: Michael Baum <michaelba@nvidia.com>
> Acked-by: Matan Azrad <matan@nvidia.com>
> ---
> drivers/net/mlx5/linux/mlx5_os.c | 56 +++------
> drivers/net/mlx5/mlx5.h | 4 +
> drivers/net/mlx5/mlx5_rxq.c | 209 +++++++++++++++++++++----------
> 3 files changed, 159 insertions(+), 110 deletions(-)
>=20
> diff --git a/drivers/net/mlx5/linux/mlx5_os.c
> b/drivers/net/mlx5/linux/mlx5_os.c
> index 70472efc29..3e496d68ea 100644
> --- a/drivers/net/mlx5/linux/mlx5_os.c
> +++ b/drivers/net/mlx5/linux/mlx5_os.c
> @@ -881,10 +881,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
> unsigned int mpls_en =3D 0;
> unsigned int swp =3D 0;
> unsigned int mprq =3D 0;
> - unsigned int mprq_min_stride_size_n =3D 0;
> - unsigned int mprq_max_stride_size_n =3D 0;
> - unsigned int mprq_min_stride_num_n =3D 0;
> - unsigned int mprq_max_stride_num_n =3D 0;
> struct rte_ether_addr mac;
> char name[RTE_ETH_NAME_MAX_LEN];
> int own_domain_id =3D 0;
> @@ -1039,15 +1035,17 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
> mprq_caps.max_single_wqe_log_num_of_strides);
> DRV_LOG(DEBUG, "\tsupported_qpts: %d",
> mprq_caps.supported_qpts);
> + DRV_LOG(DEBUG, "\tmin_stride_wqe_log_size: %d",
> + config->mprq.log_min_stride_wqe_size);
> DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
> mprq =3D 1;
> - mprq_min_stride_size_n =3D
> + config->mprq.log_min_stride_size =3D
> mprq_caps.min_single_stride_log_num_of_bytes;
> - mprq_max_stride_size_n =3D
> + config->mprq.log_max_stride_size =3D
> mprq_caps.max_single_stride_log_num_of_bytes;
> - mprq_min_stride_num_n =3D
> + config->mprq.log_min_stride_num =3D
> mprq_caps.min_single_wqe_log_num_of_strides;
> - mprq_max_stride_num_n =3D
> + config->mprq.log_max_stride_num =3D
> mprq_caps.max_single_wqe_log_num_of_strides;
> }
> #endif
> @@ -1548,36 +1546,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
> config->hw_fcs_strip =3D 0;
> DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
> (config->hw_fcs_strip ? "" : "not "));
> - if (config->mprq.enabled && mprq) {
> - if (config->mprq.log_stride_num &&
> - (config->mprq.log_stride_num >
> mprq_max_stride_num_n ||
> - config->mprq.log_stride_num <
> mprq_min_stride_num_n)) {
> - config->mprq.log_stride_num =3D
> -
> RTE_MIN(RTE_MAX(MLX5_MPRQ_DEFAULT_LOG_STRIDE_NUM,
> - mprq_min_stride_num_n),
> - mprq_max_stride_num_n);
> - DRV_LOG(WARNING,
> - "the number of strides"
> - " for Multi-Packet RQ is out of range,"
> - " setting default value (%u)",
> - 1 << config->mprq.log_stride_num);
> - }
> - if (config->mprq.log_stride_size &&
> - (config->mprq.log_stride_size > mprq_max_stride_size_n
> ||
> - config->mprq.log_stride_size < mprq_min_stride_size_n))
> {
> - config->mprq.log_stride_size =3D
> -
> RTE_MIN(RTE_MAX(MLX5_MPRQ_DEFAULT_LOG_STRIDE_SIZE,
> - mprq_min_stride_size_n),
> - mprq_max_stride_size_n);
> - DRV_LOG(WARNING,
> - "the size of a stride"
> - " for Multi-Packet RQ is out of range,"
> - " setting default value (%u)",
> - 1 << config->mprq.log_stride_size);
> - }
> - config->mprq.log_min_stride_size =3D
> mprq_min_stride_size_n;
> - config->mprq.log_max_stride_size =3D
> mprq_max_stride_size_n;
> - } else if (config->mprq.enabled && !mprq) {
> + if (config->mprq.enabled && !mprq) {
> DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
> config->mprq.enabled =3D 0;
> }
> @@ -2068,7 +2037,8 @@ mlx5_device_bond_pci_match(const char
> *ibdev_name, }
>=20
> static void
> -mlx5_os_config_default(struct mlx5_dev_config *config)
> +mlx5_os_config_default(struct mlx5_dev_config *config,
> + struct mlx5_common_dev_config *cconf)
> {
> memset(config, 0, sizeof(*config));
> config->mps =3D MLX5_ARG_UNSET;
> @@ -2080,6 +2050,10 @@ mlx5_os_config_default(struct mlx5_dev_config
> *config)
> config->vf_nl_en =3D 1;
> config->mprq.max_memcpy_len =3D
> MLX5_MPRQ_MEMCPY_DEFAULT_LEN;
> config->mprq.min_rxqs_num =3D MLX5_MPRQ_MIN_RXQS;
> + config->mprq.log_min_stride_wqe_size =3D cconf->devx ?
> + cconf-
> >hca_attr.log_min_stride_wqe_sz :
> +
> MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE;
> + config->mprq.log_stride_num =3D
> MLX5_MPRQ_DEFAULT_LOG_STRIDE_NUM;
> config->dv_esw_en =3D 1;
> config->dv_flow_en =3D 1;
> config->decap_en =3D 1;
> @@ -2496,7 +2470,7 @@ mlx5_os_pci_probe_pf(struct
> mlx5_common_device *cdev,
> uint32_t restore;
>=20
> /* Default configuration. */
> - mlx5_os_config_default(&dev_config);
> + mlx5_os_config_default(&dev_config, &cdev->config);
> dev_config.vf =3D dev_config_vf;
> list[i].eth_dev =3D mlx5_dev_spawn(cdev->dev, &list[i],
> &dev_config, ð_da);
> @@ -2666,7 +2640,7 @@ mlx5_os_auxiliary_probe(struct
> mlx5_common_device *cdev)
> if (ret !=3D 0)
> return ret;
> /* Set default config data. */
> - mlx5_os_config_default(&config);
> + mlx5_os_config_default(&config, &cdev->config);
> config.sf =3D 1;
> /* Init spawn data. */
> spawn.max_port =3D 1;
> diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index
> 4ba90db816..c01fb9566e 100644
> --- a/drivers/net/mlx5/mlx5.h
> +++ b/drivers/net/mlx5/mlx5.h
> @@ -279,6 +279,10 @@ struct mlx5_dev_config {
> unsigned int log_stride_size; /* Log size of a stride. */
> unsigned int log_min_stride_size; /* Log min size of a
> stride.*/
> unsigned int log_max_stride_size; /* Log max size of a
> stride.*/
> + unsigned int log_min_stride_num; /* Log min num of strides.
> */
> + unsigned int log_max_stride_num; /* Log max num of
> strides. */
> + unsigned int log_min_stride_wqe_size;
> + /* Log min WQE size, (size of single stride)*(num of
> strides).*/
> unsigned int max_memcpy_len;
> /* Maximum packet size to memcpy Rx packets. */
> unsigned int min_rxqs_num;
> diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c
> index e76bfaa000..891ac3d874 100644
> --- a/drivers/net/mlx5/mlx5_rxq.c
> +++ b/drivers/net/mlx5/mlx5_rxq.c
> @@ -1528,6 +1528,126 @@ mlx5_max_lro_msg_size_adjust(struct
> rte_eth_dev *dev, uint16_t idx,
> priv->max_lro_msg_size * MLX5_LRO_SEG_CHUNK_SIZE); }
>=20
> +/**
> + * Prepare both size and number of stride for Multi-Packet RQ.
> + *
> + * @param dev
> + * Pointer to Ethernet device.
> + * @param idx
> + * RX queue index.
> + * @param desc
> + * Number of descriptors to configure in queue.
> + * @param rx_seg_en
> + * Indicator if Rx segment enables, if so Multi-Packet RQ doesn't enab=
le.
> + * @param min_mbuf_size
> + * Non scatter min mbuf size, max_rx_pktlen plus overhead.
> + * @param actual_log_stride_num
> + * Log number of strides to configure for this queue.
> + * @param actual_log_stride_size
> + * Log stride size to configure for this queue.
> + *
> + * @return
> + * 0 if Multi-Packet RQ is supported, otherwise -1.
> + */
> +static int
> +mlx5_mprq_prepare(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
> + bool rx_seg_en, uint32_t min_mbuf_size,
> + uint32_t *actual_log_stride_num,
> + uint32_t *actual_log_stride_size)
> +{
> + struct mlx5_priv *priv =3D dev->data->dev_private;
> + struct mlx5_dev_config *config =3D &priv->config;
> + uint32_t log_min_stride_num =3D config->mprq.log_min_stride_num;
> + uint32_t log_max_stride_num =3D config->mprq.log_max_stride_num;
> + uint32_t log_def_stride_num =3D
> +
> RTE_MIN(RTE_MAX(MLX5_MPRQ_DEFAULT_LOG_STRIDE_NUM,
> + log_min_stride_num),
> + log_max_stride_num);
> + uint32_t log_min_stride_size =3D config->mprq.log_min_stride_size;
> + uint32_t log_max_stride_size =3D config->mprq.log_max_stride_size;
> + uint32_t log_def_stride_size =3D
> +
> RTE_MIN(RTE_MAX(MLX5_MPRQ_DEFAULT_LOG_STRIDE_SIZE,
> + log_min_stride_size),
> + log_max_stride_size);
> + uint32_t log_stride_wqe_size;
> +
> + if (mlx5_check_mprq_support(dev) !=3D 1 || rx_seg_en)
> + goto unsupport;
typo in this label name, will fix during integration.
[..]
Kindest regards
Raslan Darawsheh