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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM4PR12MB5373.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5e1ebdca-e7b1-4b2c-936a-08da7e92f77d X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Aug 2022 07:51:30.8404 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: f4ZKI1EyFHOkiUP5EoNZUY8Bl+8Go1NrO197dnaV2nKrL6HIkw3zYtMCN3ALHVOdP4ExOpOt/5i+xwK5yV78hA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4351 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org It's 20.11 LTS patch, applied and thanks! > -----Original Message----- > From: Dmitry Kozlyuk > Sent: Monday, August 15, 2022 3:27 PM > To: stable@dpdk.org > Cc: Xueming(Steven) Li ; Luca Boccassi ; Slava Ovsiienko > Subject: [PATCH] net/mlx5: fix MPRQ pool registration >=20 > mlx5_mr_update_mp() was checking pktmbuf pool private flags. > However, this function may be passed an MPRQ pool, which is not a pktmbuf= pool and has no private data. > Random data is accessed instead of pktmbuf flags, causing a crash. > Move the flags check to the RxQ start and only for pools that are known t= o be of pktmbuf type. >=20 > Fixes: 23b584d6cc85 ("net/mlx5: fix external buffer pool registration for= Rx queue") >=20 > Signed-off-by: Dmitry Kozlyuk > Acked-by: Viacheslav Ovsiienko > --- > drivers/net/mlx5/mlx5_mr.c | 11 ----------- > drivers/net/mlx5/mlx5_trigger.c | 21 +++++++++++++++++++-- > 2 files changed, 19 insertions(+), 13 deletions(-) >=20 > diff --git a/drivers/net/mlx5/mlx5_mr.c b/drivers/net/mlx5/mlx5_mr.c inde= x 1dd14ddfe5..2a7fac8ad3 100644 > --- a/drivers/net/mlx5/mlx5_mr.c > +++ b/drivers/net/mlx5/mlx5_mr.c > @@ -444,18 +444,7 @@ mlx5_mr_update_mp(struct rte_eth_dev *dev, struct ml= x5_mr_ctrl *mr_ctrl, > .mr_ctrl =3D mr_ctrl, > .ret =3D 0, > }; > - uint32_t flags =3D rte_pktmbuf_priv_flags(mp); >=20 > - if (flags & RTE_PKTMBUF_POOL_F_PINNED_EXT_BUF) { > - /* > - * The pinned external buffer should be registered for DMA > - * operations by application. The mem_list of the pool contains > - * the list of chunks with mbuf structures w/o built-in data > - * buffers and DMA actually does not happen there, no need > - * to create MR for these chunks. > - */ > - return 0; > - } > DRV_LOG(DEBUG, "Port %u Rx queue registering mp %s " > "having %u chunks.", dev->data->port_id, > mp->name, mp->nb_mem_chunks); > diff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trig= ger.c index c8dc0398ea..9b82ee40fd 100644 > --- a/drivers/net/mlx5/mlx5_trigger.c > +++ b/drivers/net/mlx5/mlx5_trigger.c > @@ -156,12 +156,29 @@ mlx5_rxq_start(struct rte_eth_dev *dev) > mlx5_mr_update_mp(dev, &rxq_ctrl->rxq.mr_ctrl, > rxq_ctrl->rxq.mprq_mp); > } else { > + struct rte_mempool *mp; > + uint32_t flags; > uint32_t s; >=20 > - for (s =3D 0; s < rxq_ctrl->rxq.rxseg_n; s++) > + /* > + * The pinned external buffer should be > + * registered for DMA operations by application. > + * The mem_list of the pool contains > + * the list of chunks with mbuf structures > + * w/o built-in data buffers > + * and DMA actually does not happen there, > + * no need to create MR for these chunks. > + */ > + for (s =3D 0; s < rxq_ctrl->rxq.rxseg_n; s++) { > + mp =3D rxq_ctrl->rxq.rxseg[s].mp; > + flags =3D rte_pktmbuf_priv_flags(mp); > + if (flags & > + RTE_PKTMBUF_POOL_F_PINNED_EXT_BUF) > + continue; > mlx5_mr_update_mp > (dev, &rxq_ctrl->rxq.mr_ctrl, > - rxq_ctrl->rxq.rxseg[s].mp); > + mp); > + } > } > ret =3D rxq_alloc_elts(rxq_ctrl); > if (ret) > -- > 2.25.1