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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM4PR12MB7549.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2f04f396-01de-4a71-a261-08dcf8161407 X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Oct 2024 12:34:48.8356 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: CCxaZkm5Yaau9RR8QzEDymPgG/OWNU+jB+J0EYP3divmy7FNxNIWIirELFho4TgyvooK/CUL6Zcq74+xXGL9Uw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4454 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Acked-by: Viacheslav Ovsiienko > -----Original Message----- > From: Alexander Kozyrev > Sent: Monday, October 28, 2024 7:54 PM > To: dev@dpdk.org > Cc: stable@dpdk.org; Raslan Darawsheh ; Slava > Ovsiienko ; Matan Azrad ; > Dariusz Sosnowski ; Bing Zhao > ; Suanming Mou > Subject: [PATCH] net/mlx5: fix shared Rx queue port number in data path >=20 > Wrong CQE is used to get the shared Rx queue port number in vectorized Rx > burst routine. Fix the CQE indexing. >=20 > Fixes: 25ed2ebff1 ("net/mlx5: support shared Rx queue port data path") >=20 > Signed-off-by: Alexander Kozyrev > --- > drivers/net/mlx5/mlx5_rxtx_vec_altivec.h | 12 ++++++------ > drivers/net/mlx5/mlx5_rxtx_vec_neon.h | 24 ++++++++++++------------ > drivers/net/mlx5/mlx5_rxtx_vec_sse.h | 6 +++--- > 3 files changed, 21 insertions(+), 21 deletions(-) >=20 > diff --git a/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h > b/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h > index cccfa7f2d3..f6e74f4180 100644 > --- a/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h > +++ b/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h > @@ -1249,9 +1249,9 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, > volatile struct mlx5_cqe *cq, > rxq_cq_to_ptype_oflags_v(rxq, cqes, opcode, &pkts[pos]); > if (unlikely(rxq->shared)) { > pkts[pos]->port =3D cq[pos].user_index_low; > - pkts[pos + p1]->port =3D cq[pos + p1].user_index_low; > - pkts[pos + p2]->port =3D cq[pos + p2].user_index_low; > - pkts[pos + p3]->port =3D cq[pos + p3].user_index_low; > + pkts[pos + 1]->port =3D cq[pos + p1].user_index_low; > + pkts[pos + 2]->port =3D cq[pos + p2].user_index_low; > + pkts[pos + 3]->port =3D cq[pos + p3].user_index_low; > } > if (rxq->hw_timestamp) { > int offset =3D rxq->timestamp_offset; > @@ -1295,17 +1295,17 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, > volatile struct mlx5_cqe *cq, > metadata; > pkts[pos]->ol_flags |=3D metadata ? flag : 0ULL; > metadata =3D rte_be_to_cpu_32 > - (cq[pos + 1].flow_table_metadata) & mask; > + (cq[pos + p1].flow_table_metadata) & mask; > *RTE_MBUF_DYNFIELD(pkts[pos + 1], offs, uint32_t > *) =3D > metadata; > pkts[pos + 1]->ol_flags |=3D metadata ? flag : 0ULL; > metadata =3D rte_be_to_cpu_32 > - (cq[pos + 2].flow_table_metadata) & mask; > + (cq[pos + p2].flow_table_metadata) & mask; > *RTE_MBUF_DYNFIELD(pkts[pos + 2], offs, uint32_t > *) =3D > metadata; > pkts[pos + 2]->ol_flags |=3D metadata ? flag : 0ULL; > metadata =3D rte_be_to_cpu_32 > - (cq[pos + 3].flow_table_metadata) & mask; > + (cq[pos + p3].flow_table_metadata) & mask; > *RTE_MBUF_DYNFIELD(pkts[pos + 3], offs, uint32_t > *) =3D > metadata; > pkts[pos + 3]->ol_flags |=3D metadata ? flag : 0ULL; diff > --git a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h > b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h > index 3ed688191f..942d395dc9 100644 > --- a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h > +++ b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h > @@ -835,13 +835,13 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, > volatile struct mlx5_cqe *cq, > rxq_cq_to_ptype_oflags_v(rxq, ptype_info, flow_tag, > opcode, &elts[pos]); > if (unlikely(rxq->shared)) { > - elts[pos]->port =3D container_of(p0, struct mlx5_cqe, > + pkts[pos]->port =3D container_of(p0, struct mlx5_cqe, > pkt_info)->user_index_low; > - elts[pos + 1]->port =3D container_of(p1, struct > mlx5_cqe, > + pkts[pos + 1]->port =3D container_of(p1, struct > mlx5_cqe, > pkt_info)->user_index_low; > - elts[pos + 2]->port =3D container_of(p2, struct > mlx5_cqe, > + pkts[pos + 2]->port =3D container_of(p2, struct > mlx5_cqe, > pkt_info)->user_index_low; > - elts[pos + 3]->port =3D container_of(p3, struct > mlx5_cqe, > + pkts[pos + 3]->port =3D container_of(p3, struct > mlx5_cqe, > pkt_info)->user_index_low; > } > if (unlikely(rxq->hw_timestamp)) { > @@ -853,34 +853,34 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, > volatile struct mlx5_cqe *cq, > ts =3D rte_be_to_cpu_64 > (container_of(p0, struct mlx5_cqe, > pkt_info)->timestamp); > - mlx5_timestamp_set(elts[pos], offset, > + mlx5_timestamp_set(pkts[pos], offset, > mlx5_txpp_convert_rx_ts(sh, ts)); > ts =3D rte_be_to_cpu_64 > (container_of(p1, struct mlx5_cqe, > pkt_info)->timestamp); > - mlx5_timestamp_set(elts[pos + 1], offset, > + mlx5_timestamp_set(pkts[pos + 1], offset, > mlx5_txpp_convert_rx_ts(sh, ts)); > ts =3D rte_be_to_cpu_64 > (container_of(p2, struct mlx5_cqe, > pkt_info)->timestamp); > - mlx5_timestamp_set(elts[pos + 2], offset, > + mlx5_timestamp_set(pkts[pos + 2], offset, > mlx5_txpp_convert_rx_ts(sh, ts)); > ts =3D rte_be_to_cpu_64 > (container_of(p3, struct mlx5_cqe, > pkt_info)->timestamp); > - mlx5_timestamp_set(elts[pos + 3], offset, > + mlx5_timestamp_set(pkts[pos + 3], offset, > mlx5_txpp_convert_rx_ts(sh, ts)); > } else { > - mlx5_timestamp_set(elts[pos], offset, > + mlx5_timestamp_set(pkts[pos], offset, > rte_be_to_cpu_64(container_of(p0, > struct mlx5_cqe, pkt_info)- > >timestamp)); > - mlx5_timestamp_set(elts[pos + 1], offset, > + mlx5_timestamp_set(pkts[pos + 1], offset, > rte_be_to_cpu_64(container_of(p1, > struct mlx5_cqe, pkt_info)- > >timestamp)); > - mlx5_timestamp_set(elts[pos + 2], offset, > + mlx5_timestamp_set(pkts[pos + 2], offset, > rte_be_to_cpu_64(container_of(p2, > struct mlx5_cqe, pkt_info)- > >timestamp)); > - mlx5_timestamp_set(elts[pos + 3], offset, > + mlx5_timestamp_set(pkts[pos + 3], offset, > rte_be_to_cpu_64(container_of(p3, > struct mlx5_cqe, pkt_info)- > >timestamp)); > } > diff --git a/drivers/net/mlx5/mlx5_rxtx_vec_sse.h > b/drivers/net/mlx5/mlx5_rxtx_vec_sse.h > index 2bdd1f676d..fb59c11346 100644 > --- a/drivers/net/mlx5/mlx5_rxtx_vec_sse.h > +++ b/drivers/net/mlx5/mlx5_rxtx_vec_sse.h > @@ -783,9 +783,9 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile > struct mlx5_cqe *cq, > rxq_cq_to_ptype_oflags_v(rxq, cqes, opcode, &pkts[pos]); > if (unlikely(rxq->shared)) { > pkts[pos]->port =3D cq[pos].user_index_low; > - pkts[pos + p1]->port =3D cq[pos + p1].user_index_low; > - pkts[pos + p2]->port =3D cq[pos + p2].user_index_low; > - pkts[pos + p3]->port =3D cq[pos + p3].user_index_low; > + pkts[pos + 1]->port =3D cq[pos + p1].user_index_low; > + pkts[pos + 2]->port =3D cq[pos + p2].user_index_low; > + pkts[pos + 3]->port =3D cq[pos + p3].user_index_low; > } > if (unlikely(rxq->hw_timestamp)) { > int offset =3D rxq->timestamp_offset; > -- > 2.43.5