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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM6PR11MB3275.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 69717aea-9f50-401d-f7ff-08da48f6f5e2 X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Jun 2022 02:31:15.0637 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 8mDxcBQK/LBkjOixURr6Vn/+eRks0+XgCSPaGWZAE8Vz2Dlr9SNaSfNPWMmbYiUHXdGsI3qAYltICn13j+ieNA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR11MB3472 X-OriginatorOrg: intel.com X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sorry that I sent the wrong mail, ignore it. > -----Original Message----- > From: Su, Simei > Sent: Wednesday, June 8, 2022 10:09 AM > To: Wu, Wenjun1 > Cc: Su, Simei ; stable@dpdk.org > Subject: [PATCH] net/ice: fix race condition for multi-cores >=20 > In multi-cores cases for Rx timestamp offload, to avoid phc time being > frequently overwritten, move related variables from ice_adapter to > ice_rx_queue structure, and each queue will handle timestamp calculation = by > itself. >=20 > Fixes: 953e74e6b73a ("net/ice: enable Rx timestamp on flex descriptor") > Fixes: 5543827fc6df ("net/ice: improve performance of Rx timestamp offloa= d") > Cc: stable@dpdk.org >=20 > Signed-off-by: Simei Su > --- > drivers/net/ice/ice_ethdev.h | 3 --- > drivers/net/ice/ice_rxtx.c | 48 ++++++++++++++++++++++----------------= ------ > drivers/net/ice/ice_rxtx.h | 3 +++ > 3 files changed, 27 insertions(+), 27 deletions(-) >=20 > diff --git a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h = index > f9f4a1c..c257bb2 100644 > --- a/drivers/net/ice/ice_ethdev.h > +++ b/drivers/net/ice/ice_ethdev.h > @@ -606,9 +606,6 @@ struct ice_adapter { > struct rte_timecounter tx_tstamp_tc; > bool ptp_ena; > uint64_t time_hw; > - uint32_t hw_time_high; /* high 32 bits of timestamp */ > - uint32_t hw_time_low; /* low 32 bits of timestamp */ > - uint64_t hw_time_update; /* SW time of HW record updating */ > struct ice_fdir_prof_info fdir_prof_info[ICE_MAX_PTGS]; > struct ice_rss_prof_info rss_prof_info[ICE_MAX_PTGS]; > /* True if DCF state of the associated PF is on */ diff --git > a/drivers/net/ice/ice_rxtx.c b/drivers/net/ice/ice_rxtx.c index > 91cdc56..71e5c6f 100644 > --- a/drivers/net/ice/ice_rxtx.c > +++ b/drivers/net/ice/ice_rxtx.c > @@ -1593,7 +1593,7 @@ ice_rx_scan_hw_ring(struct ice_rx_queue *rxq) > if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) { > uint64_t sw_cur_time =3D rte_get_timer_cycles() / (rte_get_timer_hz() > / 1000); >=20 > - if (unlikely(sw_cur_time - ad->hw_time_update > 4)) > + if (unlikely(sw_cur_time - rxq->hw_time_update > 4)) > is_tsinit =3D 1; > } > #endif > @@ -1637,16 +1637,16 @@ ice_rx_scan_hw_ring(struct ice_rx_queue *rxq) > if (unlikely(is_tsinit)) { > ts_ns =3D ice_tstamp_convert_32b_64b(hw, ad, 1, > rxq->time_high); > - ad->hw_time_low =3D (uint32_t)ts_ns; > - ad->hw_time_high =3D (uint32_t)(ts_ns >> 32); > + rxq->hw_time_low =3D (uint32_t)ts_ns; > + rxq->hw_time_high =3D (uint32_t)(ts_ns >> 32); > is_tsinit =3D false; > } else { > - if (rxq->time_high < ad->hw_time_low) > - ad->hw_time_high +=3D 1; > - ts_ns =3D (uint64_t)ad->hw_time_high << 32 | > rxq->time_high; > - ad->hw_time_low =3D rxq->time_high; > + if (rxq->time_high < rxq->hw_time_low) > + rxq->hw_time_high +=3D 1; > + ts_ns =3D (uint64_t)rxq->hw_time_high << 32 | > rxq->time_high; > + rxq->hw_time_low =3D rxq->time_high; > } > - ad->hw_time_update =3D rte_get_timer_cycles() / > + rxq->hw_time_update =3D rte_get_timer_cycles() / > (rte_get_timer_hz() / 1000); > *RTE_MBUF_DYNFIELD(mb, > ice_timestamp_dynfield_offset, @@ -1859,7 > +1859,7 @@ ice_recv_scattered_pkts(void *rx_queue, > if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) { > uint64_t sw_cur_time =3D rte_get_timer_cycles() / (rte_get_timer_hz() > / 1000); >=20 > - if (unlikely(sw_cur_time - ad->hw_time_update > 4)) > + if (unlikely(sw_cur_time - rxq->hw_time_update > 4)) > is_tsinit =3D true; > } > #endif > @@ -1979,16 +1979,16 @@ ice_recv_scattered_pkts(void *rx_queue, > rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high); > if (unlikely(is_tsinit)) { > ts_ns =3D ice_tstamp_convert_32b_64b(hw, ad, 1, > rxq->time_high); > - ad->hw_time_low =3D (uint32_t)ts_ns; > - ad->hw_time_high =3D (uint32_t)(ts_ns >> 32); > + rxq->hw_time_low =3D (uint32_t)ts_ns; > + rxq->hw_time_high =3D (uint32_t)(ts_ns >> 32); > is_tsinit =3D false; > } else { > - if (rxq->time_high < ad->hw_time_low) > - ad->hw_time_high +=3D 1; > - ts_ns =3D (uint64_t)ad->hw_time_high << 32 | > rxq->time_high; > - ad->hw_time_low =3D rxq->time_high; > + if (rxq->time_high < rxq->hw_time_low) > + rxq->hw_time_high +=3D 1; > + ts_ns =3D (uint64_t)rxq->hw_time_high << 32 | > rxq->time_high; > + rxq->hw_time_low =3D rxq->time_high; > } > - ad->hw_time_update =3D rte_get_timer_cycles() / > + rxq->hw_time_update =3D rte_get_timer_cycles() / > (rte_get_timer_hz() / 1000); > *RTE_MBUF_DYNFIELD(rxm, > (ice_timestamp_dynfield_offset), @@ -2369,7 > +2369,7 @@ ice_recv_pkts(void *rx_queue, > if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) { > uint64_t sw_cur_time =3D rte_get_timer_cycles() / (rte_get_timer_hz() > / 1000); >=20 > - if (unlikely(sw_cur_time - ad->hw_time_update > 4)) > + if (unlikely(sw_cur_time - rxq->hw_time_update > 4)) > is_tsinit =3D 1; > } > #endif > @@ -2430,16 +2430,16 @@ ice_recv_pkts(void *rx_queue, > rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high); > if (unlikely(is_tsinit)) { > ts_ns =3D ice_tstamp_convert_32b_64b(hw, ad, 1, > rxq->time_high); > - ad->hw_time_low =3D (uint32_t)ts_ns; > - ad->hw_time_high =3D (uint32_t)(ts_ns >> 32); > + rxq->hw_time_low =3D (uint32_t)ts_ns; > + rxq->hw_time_high =3D (uint32_t)(ts_ns >> 32); > is_tsinit =3D false; > } else { > - if (rxq->time_high < ad->hw_time_low) > - ad->hw_time_high +=3D 1; > - ts_ns =3D (uint64_t)ad->hw_time_high << 32 | > rxq->time_high; > - ad->hw_time_low =3D rxq->time_high; > + if (rxq->time_high < rxq->hw_time_low) > + rxq->hw_time_high +=3D 1; > + ts_ns =3D (uint64_t)rxq->hw_time_high << 32 | > rxq->time_high; > + rxq->hw_time_low =3D rxq->time_high; > } > - ad->hw_time_update =3D rte_get_timer_cycles() / > + rxq->hw_time_update =3D rte_get_timer_cycles() / > (rte_get_timer_hz() / 1000); > *RTE_MBUF_DYNFIELD(rxm, > (ice_timestamp_dynfield_offset), diff --git > a/drivers/net/ice/ice_rxtx.h b/drivers/net/ice/ice_rxtx.h index > bb18a01..f5337d5 100644 > --- a/drivers/net/ice/ice_rxtx.h > +++ b/drivers/net/ice/ice_rxtx.h > @@ -95,6 +95,9 @@ struct ice_rx_queue { > uint32_t time_high; > uint32_t hw_register_set; > const struct rte_memzone *mz; > + uint32_t hw_time_high; /* high 32 bits of timestamp */ > + uint32_t hw_time_low; /* low 32 bits of timestamp */ > + uint64_t hw_time_update; /* SW time of HW record updating */ > }; >=20 > struct ice_tx_entry { > -- > 2.9.5