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charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.29 Subject: Re: [dpdk-stable] [PATCH] net/mlx5: remove unwanted barrier X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Hi, Honnappa The rte_io_rmb() was inserted not to prevent the extra access to cqe->op_ow= n (the volatile qualifier is quite enough, if we had some doubts, we would in= sert rte_compiler_barrier), but the real intention of io_rmw was to isolate cqe->op_own loads on hardwa= re level. cqe points to the Completion Queue Entry (CQE), that is mapped to the memor= y that is continuously being updated by the device (NIC). CQE is 64B size structure and op_own is = located at the structure end, and is updated by HW in last order, after the entire CQE is completely writ= ten to the host memory. After detecting by cqe_check() the CQE is owned by software (hardware compl= eted operation) the PMD starts touching other CQE fields, i.e. the next load transactions f= rom CQE are triggered. And we must make sure these loads happen in correct order, only if cqe->op_= own load was completed and valid ownership flags were seen, i.e. - do not allow speculative reads with= possible incorrect values fetched). Just hypothetical case (I agree in advance - it is very unlikely, but is no= t impossible :)): 1. owner =3D cqe->op_own - load A triggered 2. some code is being speculatively executed, no barrier 3. length =3D cqe->length - load B triggered 4. Let's suppose CPU reordered A and B, ie order of loads: B, A 5. In memory/CPU cache we have old CQE, owned by HW 6. B load gets the old length value (invalid) 7. Hardware writes the new CQE and CPU cache is invalidated 8. A load gets the CQE is owned by SW and the invalid results of load B wil= l be used by PMD Hence, I would consider the patch as risky, and as one that is extremely ha= rd to be covered completely with tests - we should test for race conditions on multiple architectures, on many CPU m= odels, PCIe root complexes, etc. With best regards, Slava > -----Original Message----- > From: Honnappa Nagarahalli > Sent: Sunday, June 6, 2021 19:50 > To: dev@dpdk.org; honnappa.nagarahalli@arm.com; Matan Azrad > ; Shahaf Shuler ; Slava Ovsiienko > > Cc: ruifeng.wang@arm.com; Matan Azrad ; > stable@dpdk.org > Subject: [PATCH] net/mlx5: remove unwanted barrier >=20 > The IO barrier is not required as cqe->op_own is read once. The checks do= ne on > the local variable and the memory is not read again. >=20 > Fixes: 88c0733535d6 ("net/mlx5: extend Rx completion with error handling"= ) > Cc: matan@mellanox.com > Cc: stable@dpdk.org >=20 > Signed-off-by: Honnappa Nagarahalli > Reviewed-by: Ruifeng Wang > --- > drivers/common/mlx5/mlx5_common.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >=20 > diff --git a/drivers/common/mlx5/mlx5_common.h > b/drivers/common/mlx5/mlx5_common.h > index 5028a05b49..a4c29f51f1 100644 > --- a/drivers/common/mlx5/mlx5_common.h > +++ b/drivers/common/mlx5/mlx5_common.h > @@ -195,7 +195,7 @@ check_cqe(volatile struct mlx5_cqe *cqe, const > uint16_t cqes_n, >=20 > if (unlikely((op_owner !=3D (!!(idx))) || (op_code =3D=3D > MLX5_CQE_INVALID))) > return MLX5_CQE_STATUS_HW_OWN; > - rte_io_rmb(); > + > if (unlikely(op_code =3D=3D MLX5_CQE_RESP_ERR || > op_code =3D=3D MLX5_CQE_REQ_ERR)) > return MLX5_CQE_STATUS_ERR; > -- > 2.17.1