From: Slava Ovsiienko <viacheslavo@nvidia.com>
To: Ali Alnubani <alialnu@nvidia.com>,
Ruifeng Wang <ruifeng.wang@arm.com>,
Matan Azrad <matan@nvidia.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>,
"honnappa.nagarahalli@arm.com" <honnappa.nagarahalli@arm.com>,
"stable@dpdk.org" <stable@dpdk.org>, "nd@arm.com" <nd@arm.com>
Subject: RE: [PATCH] net/mlx5: fix risk in Rx descriptor read in NEON vector path
Date: Mon, 20 Jun 2022 05:37:54 +0000 [thread overview]
Message-ID: <DM6PR12MB3753981B0745993CAE13B0B7DFB09@DM6PR12MB3753.namprd12.prod.outlook.com> (raw)
In-Reply-To: <DM4PR12MB516707642A2AD5AFDCA64892DAD09@DM4PR12MB5167.namprd12.prod.outlook.com>
Hi, Ruifeng
My apologies for review delay.
As far I understand the hypothetical problem scenario is:
- CPU core reorders reading of qwords of 16B vector
- core reads the second 8B of CQE (old CQE values)
- CQE update
- core reads the first 8B of CQE (new CQE values)
How the re-reading of CQEs can resolve the issue?
This wrong scenario might happen on the second read
and we would run into the same issue.
In my opinion, the right solution to cover potential reordering should be:
- read CQE
- check CQE status (first 8B)
- read memory barrier
- read the rest of CQE
With best regards,
Slava
> -----Original Message-----
> From: Ali Alnubani <alialnu@nvidia.com>
> Sent: Thursday, May 19, 2022 17:56
> To: Ruifeng Wang <ruifeng.wang@arm.com>; Matan Azrad
> <matan@nvidia.com>; Slava Ovsiienko <viacheslavo@nvidia.com>
> Cc: dev@dpdk.org; honnappa.nagarahalli@arm.com; stable@dpdk.org;
> nd@arm.com
> Subject: RE: [PATCH] net/mlx5: fix risk in Rx descriptor read in NEON vector
> path
>
> > -----Original Message-----
> > From: Ruifeng Wang <ruifeng.wang@arm.com>
> > Sent: Tuesday, January 4, 2022 5:01 AM
> > To: Matan Azrad <matan@nvidia.com>; Slava Ovsiienko
> > <viacheslavo@nvidia.com>
> > Cc: dev@dpdk.org; honnappa.nagarahalli@arm.com; stable@dpdk.org;
> > nd@arm.com; Ruifeng Wang <ruifeng.wang@arm.com>
> > Subject: [PATCH] net/mlx5: fix risk in Rx descriptor read in NEON
> > vector path
> >
> > In NEON vector PMD, vector load loads two contiguous 8B of descriptor
> > data into vector register. Given vector load ensures no 16B atomicity,
> > read of the word that includes op_own field could be reordered after
> > read of other words. In this case, some words could contain invalid
> > data.
> >
> > Reloaded qword0 after read barrier to update vector register. This
> > ensures that the fetched data is correct.
> >
> > Testpmd single core test on N1SDP/ThunderX2 showed no performance
> > drop.
> >
> > Fixes: 1742c2d9fab0 ("net/mlx5: fix synchronization on polling Rx
> > completions")
> > Cc: stable@dpdk.org
> >
> > Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
> > ---
>
> Tested with BlueField-2 and didn't see a performance impact.
>
> Tested-by: Ali Alnubani <alialnu@nvidia.com>
>
> Thanks,
> Ali
next prev parent reply other threads:[~2022-06-20 5:37 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-04 3:00 Ruifeng Wang
2022-02-10 6:24 ` Ruifeng Wang
2022-02-10 8:16 ` Slava Ovsiienko
2022-02-10 8:29 ` Ruifeng Wang
2022-05-19 14:56 ` Ali Alnubani
2022-06-20 5:37 ` Slava Ovsiienko [this message]
2022-06-27 11:08 ` Ruifeng Wang
2022-06-29 7:55 ` Slava Ovsiienko
2022-06-29 11:41 ` Ruifeng Wang
2022-09-29 6:51 ` Ruifeng Wang
2023-03-07 16:59 ` Slava Ovsiienko
2023-05-30 5:48 ` [PATCH v2] " Ruifeng Wang
2023-06-19 12:13 ` Raslan Darawsheh
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