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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM6PR12MB3753.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: b8d90c4e-cca7-442c-7d93-08da59a4b602 X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Jun 2022 07:55:18.9159 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: RajpA6UrB7zpLXWqH01iddo+hCvVTl11ygL+itkpU1p2MOAfj4KoF02msT7mfCQGBpwvRbliF4g20ShFzfx5og== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4923 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, Ruifeng > -----Original Message----- > From: Ruifeng Wang > Sent: Monday, June 27, 2022 14:08 > To: Slava Ovsiienko ; Ali Alnubani > ; Matan Azrad > Cc: dev@dpdk.org; Honnappa Nagarahalli ; > stable@dpdk.org; nd ; nd > Subject: RE: [PATCH] net/mlx5: fix risk in Rx descriptor read in NEON > vector path >=20 > > -----Original Message----- > > From: Slava Ovsiienko > > Sent: Monday, June 20, 2022 1:38 PM > > To: Ali Alnubani ; Ruifeng Wang > > ; Matan Azrad > > Cc: dev@dpdk.org; Honnappa Nagarahalli ; > > stable@dpdk.org; nd > > Subject: RE: [PATCH] net/mlx5: fix risk in Rx descriptor read in NEON > > vector path > > > > Hi, Ruifeng >=20 > Hi Slava, >=20 > Thanks for your review. > > > > My apologies for review delay. >=20 > Apologies too. I was on something else. >=20 > > As far I understand the hypothetical problem scenario is: > > - CPU core reorders reading of qwords of 16B vector > > - core reads the second 8B of CQE (old CQE values) > > - CQE update > > - core reads the first 8B of CQE (new CQE values) >=20 > Yes, This is the problem. > > > > How the re-reading of CQEs can resolve the issue? > > This wrong scenario might happen on the second read and we would run > > into the same issue. >=20 > Here we are trying to ordering reading of a 16B vector (8B with op_own - > high, and 8B without op_own - low). > The first read will load 16B. The second read will load and update low > 8B (no op_own). OK, I got the point, thank you for the explanations. Can we avoid the first reading of low 8B (no containing CQE owning field)?= =20 I mean to update this part to read only upper 8Bs: /* B.0 (CQE 3) load a block having op_own. */ c3 =3D vld1q_u64((uint64_t *)(p3 + 48)); /* B.0 (CQE 2) load a block having op_own. */ c2 =3D vld1q_u64((uint64_t *)(p2 + 48)); /* B.0 (CQE 1) load a block having op_own. */ c1 =3D vld1q_u64((uint64_t *)(p1 + 48)); /* B.0 (CQE 0) load a block having op_own. */ c0 =3D vld1q_u64((uint64_t *)(p0 + 48)); /* Synchronize for loading the rest of blocks. */ rte_io_rmb(); Because lower 8Bs will be overlapped with the second read (in your patch)=20 and barrier ensures the correct order. With best regards, Slava