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DIR:OUT; SFP:1101; SCL:1; SRVR:HE1PR0701MB2489; H:HE1PR0701MB2394.eurprd07.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: ericsson.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: 3Af8A+oj8q/qSKbooTWtHWOE+pol/dU++VyvVp43J5R5jk43f7ILimz4SxkZ7P4xpORCALm1FQcKCruPu5XIqddvcA2WLpGJg6ABQTDaYgBC0RxUCAV+f4cfm7r/Yg6snk1JE+qv1B3oD8cmfVjwwyI2rhH7xFSpo4ulzuDzuG8qWKP7rX5kpRAhjX79QyFrbJg/H00/wDkoyLri3O1xDaWmIZ8tZvIB2QIfDvuft6cXOrY+xymJbbJQQe2uBQWVAhFp27FtSorg8zd5wPtLpDq3QTdYmiuBXOHskSQM6ZrxbWSyVxBIG/gXBngD+AJ0sjlVAVU0d+DL2p5XgURGhQF6lpO9Kj0wj+aM/pwELEc= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: ccc7f2dc-c3f3-4b5c-b76d-08d641c8b559 X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Nov 2018 20:12:40.9632 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 92e84ceb-fbfd-47ab-be52-080c6b87953f X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR0701MB2489 X-OriginatorOrg: ericsson.com X-Brightmail-Tracker: H4sIAAAAAAAAA02Sf0yMcRzH931+3D0dN1/p6rNytk7MqJTCM1n5vYdhzEY/V4dHRV12V+dX f0QtZFbh5FjSIStp1dVqhInozOJoc/2QSlGhWqlIk56es/nv9f6+P3t9P/vuy5COFtqVidUk 8lqNOk4lkVHG4Cq9VwBqC/Mx5q9ibUVB7KjxNMH2D1URrKWnD7HG7jQpm33Bnx2YMFHs6TPP aLbyVBnB/jkzIWWH2uupNTM4a2Yr4oqvFyOutD6T5sZv3Ka5mzW9BNdea6a4502XpTukobLV +/m4WD2vXRoYJYvpLzaTh784H+20NRIpyDw7AzEMYH8wlDllIBnjiJ8hKHiZRothBEGnadge bhLQ1HkKCYHCWSScv1eFxOYyAXfTu0gxfEaQ0lJHZCAHRoI3w1hPOimwEw6B79mThDBE4lck DJx8QQvFHLwbRq0F9qE9UHn2GiHyMnh4rlAqMIU9IM30ixK2leMoePTcT7zMgGDEekUizDjg hVDSaJt2IqyEj2NtlMAkdoHmrrxpJ2AMt2pekyIroPfTH1pwoilnTt128dgd3tT0SUVWwtu8 c0hkmwRGy8NF9oJBg8Gu2Qa5T0unXwKwBYGxd5ISC0/IafhpFyWA6VqFXRQBJVcf0CLPg6Lz HVQW8r3636oie4PNcEki8hIoyP9KCizHs8Fi7KJuIKoIKXS8bm989DI/b14bu0+nS9B4a/jE cjT1wZ5U/F5Qjd59W1uLMINUM+XpPz6EOdJqve5YfC0ChlQ5yX81TB3J96uPHee1CZHapDhe V4vcGErlIu9YaQ51xNHqRP4Qzx/mtf9agnFwTUHZbQ27NuVLIzeeLB2+3Xqgedawmdm6YnlL r6l7PHiQCRgY2jJ6Z12pm3RQ46PUb148xlUfvJhwJDd3fqZz6vYga+uw4m2cRx4eCSnM2uue U50ceMLqHd6RWrjh+Nn3OwlqkceRgIaWwPqkx3XuvqGeSkXE5PrI8t3c3KHqRZbi+8kqShej 9l1ManXqv+VATHZcAwAA Subject: Re: [dpdk-stable] [dpdk-dev] [PATCH 1/2] ring: synchronize the load and store of the tail X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 03 Nov 2018 20:12:44 -0000 > -----Original Message----- > From: dev On Behalf Of Thomas Monjalon > Sent: den 27 oktober 2018 17:13 > To: Jerin Jacob > Cc: Gavin Hu (Arm Technology China) ; dev@dpdk.org; > Honnappa Nagarahalli ; > stable@dpdk.org; Ola Liljedahl ; > olivier.matz@6wind.com; chaozhu@linux.vnet.ibm.com; > bruce.richardson@intel.com; konstantin.ananyev@intel.com > Subject: Re: [dpdk-dev] [PATCH 1/2] ring: synchronize the load and store = of > the tail >=20 > 27/10/2018 17:00, Jerin Jacob: > > From: Thomas Monjalon > > > 17/10/2018 08:35, Gavin Hu (Arm Technology China): > > > > Hi Jerin > > > > > > > > As the 1st one of the 3-patch set was not concluded, I submit this = 2- > patch series to unblock the merge. > > > > > > The thread is totally messed up because: > > > - there is no cover letter > > > - some different series (testpmd, i40e and doc) are in the sa= me > thread > > > - v4 replies to a different series > > > - this version should be a v5 but has no number > > > - this version replies to the v3 > > > - patchwork still shows v3 and "v5" > > > - replies from Ola are not quoting previous discussion > > > > > > Because of all of this, it is really difficult to follow. > > > This is probably the reason of the lack of review outside of Arm. > > > > > > One more issue: you must Cc the relevant maintainers. > > > Here: > > > - Olivier for rte_ring > > > - Chao for IBM platform > > > - Bruce and Konstantin for x86 > > > > > > Guys, it is really cool to have more Arm developpers in DPDK. > > > But please consider better formatting your discussions, it is really > > > important in our contribution workflow. > > > > > > I don't know what to do. > > > I suggest to wait for more feedbacks and integrate it in -rc2. > > > > This series has been acked and tested. Sure, if we are looking for > > some more feedback we can push to -rc2 if not it a good candidate to > > be selected for -rc1. >=20 > It has been acked and tested only for Arm platforms. > And Olivier, the ring maintainer, was not Cc. >=20 > I feel it is not enough. >=20 I've just run an out-of-tree test program I have for the DSW scheduler, whi= ch verify scheduler atomic semantics. The results are: Non-C11 mode: pass C11 mode before this patch set: fail C11 mode after this patch set: pass This suggests the current C11 mode is broken even on x86_64. I haven't been= following this thread closely, so maybe this is known already. I've also run an out-of-tree DSW throughput benchmark, and I've found that = going from Non-C11 to C11 gives a 4% slowdown. After this patch, the slowdo= wn is only 2,8%. GCC 7.3.0 and a Skylake x86_64.