From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 36B5241E1B for ; Wed, 8 Mar 2023 07:00:30 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 278BB410FB; Wed, 8 Mar 2023 07:00:30 +0100 (CET) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mails.dpdk.org (Postfix) with ESMTP id A64F640E03; Wed, 8 Mar 2023 07:00:26 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678255227; x=1709791227; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=+Jj/RTorOWM8QnYUJg1VNA6ctXGL9ZyTGLZWyqtATrU=; b=YKnEPS0WpDbjyP3rhFNdsKkWTY4aOsfe70mHxJK4HkeG+XXdolz4thq3 eAP4r9JoJwy0O7RdP22r3MttIIRfOF6ldXzL2ZthOJ4PpNqprBVpp0BmD AetOlvr5O8YxczWPntf5fgb49Mzmbqz+hYfmV2D7NHS3PAV7zEwaXPQyy 2hHOhHX2Ftc0+GRo1Ec+wkdl5jee0Hnck/fyReKh/bIoaoQQHKGFALxSJ w0Sj7HcAjs8lZSm1wAMDEqgI7X1JaQ+11DDuBhaP1HiUCpejVSkMBqtoe cjeTqaZ2uBX09Dbth//0LPpto+qkFPjOClBtjD44nurT14HMZ5sVIsjIC A==; X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="336090002" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="336090002" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2023 22:00:25 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="1006179761" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="1006179761" Received: from fmsmsx602.amr.corp.intel.com ([10.18.126.82]) by fmsmga005.fm.intel.com with ESMTP; 07 Mar 2023 22:00:25 -0800 Received: from fmsmsx612.amr.corp.intel.com (10.18.126.92) by fmsmsx602.amr.corp.intel.com (10.18.126.82) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Tue, 7 Mar 2023 22:00:25 -0800 Received: from fmsmsx611.amr.corp.intel.com (10.18.126.91) by fmsmsx612.amr.corp.intel.com (10.18.126.92) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Tue, 7 Mar 2023 22:00:24 -0800 Received: from FMSEDG603.ED.cps.intel.com (10.1.192.133) by fmsmsx611.amr.corp.intel.com (10.18.126.91) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21 via Frontend Transport; Tue, 7 Mar 2023 22:00:24 -0800 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (104.47.55.175) by edgegateway.intel.com (192.55.55.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.21; Tue, 7 Mar 2023 22:00:24 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=PDd6Ik45eNCJNSEE2GxNKbI2fJXh2jIbUFjUmiJeBbte2/4KxLdQZyvGSpeVqjJlHVePqRoujblTA3kE42BLY5q7MkZ2doPujRNuilVRYnkxASFS6chCA40xhLV3FAictuqcOYH1LazsvpMc8r8NPsF0xi2bVofEXivyQpXQfj6wIQPGUu3jmuHdtwGaCMHNm3ZEZ3ygWQSh6ZRvuYX5p1lQfzk3QcaPEMWBIl9LjMJ2lurZ2W36r69vL6sEuWr8VWchQX9mcAfv+AFwpdNMzoqFbVWbzqMoG99vk2r+1jQ0ax/+zYliw5/lLYWLbJ90qMD7/j8NiTGuQAkgvLLdtQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=w8xWxZ+L9q3ZjYAQbA16SrKXBqlValHSW7HdNXnAHsg=; b=RH3RJk4VjUcrBb9kebZ+EGy0kyTvzULMDZgYVwr3TqgPpdvrGt0BJICo904bId/I/xNgtqZhnV5E2NkRVAw917mXDdtsRGqyOtkeAUgdAXgfw86RJKPvZKXzO8Zl2N/um1pr/ZenA9WyDa6s9Ve4wlyPPVh0xpuPGD3Mn4VIsEqomkhYjAtV4AJNtQYItr4zWyH8ZX4FuYWW7PPAQ1BvYagfTq82i/QO43ludnscy8WzujghDZ1nW1tbHbxCipOgwb/ZkYBtIGGq1sxlusKmqEd860+Z6NSeLNLOvMffDrIhWkHc4efAJFmAuZc3ufW0/ZO7DHrDGiA7dLJVRzRbNA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Received: from IA0PR11MB7955.namprd11.prod.outlook.com (2603:10b6:208:3dd::6) by IA0PR11MB7790.namprd11.prod.outlook.com (2603:10b6:208:403::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6156.28; Wed, 8 Mar 2023 06:00:17 +0000 Received: from IA0PR11MB7955.namprd11.prod.outlook.com ([fe80::726b:b206:dfd5:34ac]) by IA0PR11MB7955.namprd11.prod.outlook.com ([fe80::726b:b206:dfd5:34ac%6]) with mapi id 15.20.6156.029; Wed, 8 Mar 2023 06:00:17 +0000 From: "Wu, Wenjun1" To: "Su, Simei" , "Zhang, Qi Z" , "Yang, Qiming" CC: "dev@dpdk.org" , "stable@dpdk.org" Subject: RE: [PATCH v2] net/ice: fix incorrect Rx timestamp Thread-Topic: [PATCH v2] net/ice: fix incorrect Rx timestamp Thread-Index: AQHZUXfNdntKWOaHIEyrMixc9WoOl67wVfQQ Date: Wed, 8 Mar 2023 06:00:16 +0000 Message-ID: References: <20230302134501.201032-1-simei.su@intel.com> <20230308043655.324241-1-simei.su@intel.com> In-Reply-To: <20230308043655.324241-1-simei.su@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: IA0PR11MB7955:EE_|IA0PR11MB7790:EE_ x-ms-office365-filtering-correlation-id: bcec845c-01b6-4f38-3bb0-08db1f9a6417 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: j8G1zUwGGqMMLus4mcy2ohHlrJPOoKgYKB+NJxDgGervyoVTzFsL4TMGomhC+YDUwp7uwx4RTkCNm8oGW0g93e4bGtUuyRfnYcAG6YbMjFb8fVkHT8RpPQJSXgLM7Ba48zj90u9Ts/WSmMlzGppDKTjjcb9qFk94ujelLkHBIWFKI771XbhTm6cbPedBaiq124M5K1BK/QN1Do7PKZH55s55zgLdVujg7LO+YSxZxu3ywQ20bJvL19Qa91TH1fdDQpFDT3UkEnxtdkSWjW3GO5bvxV4rOqM55/ytgvGjuPB9qsZ24XtKJin3XR5jwYH9WGot5rJ4DjHevItN/ChRxEaxqaWR4ED7MAwFjXZnO6FkuuR9ARfXWI92CCc2IJrrbi3paCisj2/6jdMH1vPEAHFeImLya9VtDkaxn3a9oovdOOpTQLghnXicf0IGFbNffm5QgElqGBe4mTPo8bG+84gBmOpdEI2G/WIKKla2o3MzOzjQJhSnpLfK5nkDoHw1KBBs158DltMFQEkvl2zAUL9UOMb02qIi9q9xBnrXxxySvSNq8I6lGj1JAxGGbgW3GQm6jfPw2Wnl6+iDVahfkW++uVeSQZZETbHCipqFzEQu4KvkWTzAetQcuPXy3fcH9ssjpZC8E6Vqq93Vh6pbvk4HVurzDc1KJdC5ZwGECyjjxb0PISL1YEeEE6DKMvB0UHv/dLTyKMKHLT4o6yYFyg== x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:IA0PR11MB7955.namprd11.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230025)(39860400002)(376002)(396003)(346002)(366004)(136003)(451199018)(66476007)(4326008)(76116006)(8936002)(66446008)(41300700001)(64756008)(8676002)(66556008)(66946007)(5660300002)(2906002)(38070700005)(82960400001)(122000001)(86362001)(38100700002)(33656002)(26005)(7696005)(6506007)(71200400001)(450100002)(6636002)(110136005)(55016003)(478600001)(316002)(52536014)(54906003)(83380400001)(186003)(9686003)(53546011); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?E01SvDoHsTDxwM7krP5B5yf+0UeGFhe4exWjeOkhjRPTenf0HBcA+8MXU1s3?= =?us-ascii?Q?nL3acskLhjLrIFZtxUEQS9bDN96/DvPeUUhp0bHPyumcUchYuV7rOybdKJFR?= =?us-ascii?Q?pjrkbvqZQvmjcBikJRGZsyGwRCYg2DPbhq9iRupz8nXbunn5ObIrbpbYVOqh?= =?us-ascii?Q?R5QuP5unVgDZ/qpLAVx5gFmFsZ1kLfd+VkLnP4pWToYEHCF3WP+5XztpdVpF?= =?us-ascii?Q?Qje1m4b8NyftS0yVsTTB7pg4YHSM9uFkOzYeeYdjWpfdkcJXAQNHhObAz0SX?= =?us-ascii?Q?JCpVEnuufqQqH+SQohi33QPY7AkDSejFMNA9XpMPaRWzWE20pN+HgTgBcw7G?= =?us-ascii?Q?5t4sompXR7AfLWslRvkQ/t9/u6J+b6oDJcOwY8Fn5sSY/3UjvpkP2Rk9XYsd?= =?us-ascii?Q?MB5GZ5zbj3dd2NSB00QmjGBM+gCehdb6/V+yleo9Dd3Gl22+G5PVvNdo7Zj/?= =?us-ascii?Q?q6Xe3TwbT9WlLiawbVkbIQvCMmywzjKyxx22bntptbX6QSv5Bhy1eBsFvuTV?= =?us-ascii?Q?29MspibPGsNApOi3Zn1cRGTYAaji40pPaetrVpj8k6cV4Zr7HbqrT3GwAkDO?= =?us-ascii?Q?sHJWPbrxMkzbCNrxcS/XsZk6+P+hXgV/K+vajz6pa6pCuoQVDEcs2sGRKIS+?= =?us-ascii?Q?cT+Wqcc6AuGI/7wvfoU1OJV2YLxaO8QQi7Aw5rfl4U6AjS0WBPexyOqHw4w9?= =?us-ascii?Q?BPgGm8DwmfQTFqa0V0+Q6ERj5zmZk95JCFKs9/V/OMESbyjhKuaYjyBnQAY3?= =?us-ascii?Q?f+bhHO1D+QCgyV2+sbjqEJ/wJnvLY6kYYUY0ggD9W1YSZUIeAU6+YGMx9iOF?= =?us-ascii?Q?OUIc5Rjr7P28WU7Z5MI8TmcIGLIY2cNn+qowzh3YnFHlJUYxGbpuHh1XLs8j?= =?us-ascii?Q?Aif9nzbFkslL4PWv2IP/68+2koExAPK9cGUaSMvj39iOrq8bG3c/k7lPNipf?= =?us-ascii?Q?/i7wXMBPvR3V2LdWhP0dgxCFuNUpV/9iUBPjCCKI9wEkmUH2vt2Dj1rRp0Cb?= =?us-ascii?Q?oFYw6ROOQ5owaQrGuPdtEcwqEt6iDXS3bgpa7B1rLXcJJOTPaUSHtloUAlaw?= =?us-ascii?Q?kx+PW0yzaPVcR0wKUgsO2NwKnAD46Vqc1jMVfKgD6slYtdHbbRZHXbdXTxqR?= =?us-ascii?Q?IX0MgWi13WRyLFNdZA/WzwbqZaeuc/wCeUkfYIqyrqU5ans/cLLGfNkOZxsw?= =?us-ascii?Q?2/2IFhWgBjjG/hphXhB/3AhMo58JqNEwoeRa+fMiNURRoIqfc3W0gMWSwysh?= =?us-ascii?Q?tnCxLsJyRJ+u+1hFOuuQq42e4/HSTHy1RgJjTkvo6XafyJyH+X8y9Iep/gF3?= =?us-ascii?Q?eNCXqdMQMeTKSFSFT5Sy6Mv6uNFHMXw+70RnlDnifFdjvOIQAKSSMiNBev7p?= =?us-ascii?Q?QwsKq9VUtt2BJRrbmi4V/g6pBEGzyQpHp5z4Auc25WHBiX8iJysqIgxP2YZC?= =?us-ascii?Q?tFHe2Cswus3ofM9ET+tRlDO4EVpmrONRp6X5K1IMJoFA5nHgMMLWESW+KV+l?= =?us-ascii?Q?fVBVzO0LxoWYQx0mj8Q9A0gAMzXtsiaM27ZylQr8jS0LkFrt1qj9wnlZ62L1?= =?us-ascii?Q?7Yp1oxAMwXoNY8S1eMa2xCdAZjetb1HcownQiN1w?= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: IA0PR11MB7955.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: bcec845c-01b6-4f38-3bb0-08db1f9a6417 X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Mar 2023 06:00:16.7569 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: C6/bNNwejxSAmz+zlEw4Y5+oKLpru3XmTjFcZEeHjFjNS8Vnwah7U6HuaRzNkdNBJymK+B8PFjXkI2+lBM6TlQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR11MB7790 X-OriginatorOrg: intel.com X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org > -----Original Message----- > From: Su, Simei > Sent: Wednesday, March 8, 2023 12:37 PM > To: Zhang, Qi Z ; Yang, Qiming > > Cc: dev@dpdk.org; Wu, Wenjun1 ; Su, Simei > ; stable@dpdk.org > Subject: [PATCH v2] net/ice: fix incorrect Rx timestamp >=20 > For E822, the time value in Rx Flex Descriptors is 0 due to the missing P= HY > clock timer setup. Also, the source clock index in use is based on device > capabilities instead of always being zero. >=20 > Fixes: 953e74e6b73a ("net/ice: enable Rx timestamp on flex descriptor") > Fixes: 646dcbe6c701 ("net/ice: support IEEE 1588 PTP") > Fixes: fb800fde66f4 ("net/ice/base: work around missing PTP capabilities"= ) > Cc: stable@dpdk.org >=20 > Signed-off-by: Simei Su > --- > v2: > * Refine commit title and commit log. > * Remove duplicate code. > * Rework share code for "SIMICS_SUPPORT". >=20 > drivers/net/ice/base/ice_common.c | 4 +--- > drivers/net/ice/ice_ethdev.c | 36 ++++++++++++++++++++++-----------= --- > drivers/net/ice/ice_rxtx.h | 11 ++++++----- > 3 files changed, 29 insertions(+), 22 deletions(-) >=20 > diff --git a/drivers/net/ice/base/ice_common.c > b/drivers/net/ice/base/ice_common.c > index 5391bd6..1a02aad 100644 > --- a/drivers/net/ice/base/ice_common.c > +++ b/drivers/net/ice/base/ice_common.c > @@ -2554,9 +2554,7 @@ ice_parse_1588_func_caps(struct ice_hw *hw, > struct ice_hw_func_caps *func_p, > struct ice_aqc_list_caps_elem *cap) { > struct ice_ts_func_info *info =3D &func_p->ts_func_info; > - u32 number =3D ICE_TS_FUNC_ENA_M | ICE_TS_SRC_TMR_OWND_M | > - ICE_TS_TMR_ENA_M | ICE_TS_TMR_IDX_OWND_M | > - ICE_TS_TMR_IDX_ASSOC_M; > + u32 number =3D LE32_TO_CPU(cap->number); > u8 clk_freq; >=20 > ice_debug(hw, ICE_DBG_INIT, "1588 func caps: raw value %x\n", > number); diff --git a/drivers/net/ice/ice_ethdev.c > b/drivers/net/ice/ice_ethdev.c index 0d011bb..9a88cf9 100644 > --- a/drivers/net/ice/ice_ethdev.c > +++ b/drivers/net/ice/ice_ethdev.c > @@ -2413,6 +2413,17 @@ ice_dev_init(struct rte_eth_dev *dev) > /* Initialize TM configuration */ > ice_tm_conf_init(dev); >=20 > + if (ice_is_e810(hw)) > + hw->phy_cfg =3D ICE_PHY_E810; > + else > + hw->phy_cfg =3D ICE_PHY_E822; > + > + if (hw->phy_cfg =3D=3D ICE_PHY_E822) { > + ret =3D ice_start_phy_timer_e822(hw, hw->pf_id, true); > + if (ret) > + PMD_INIT_LOG(ERR, "Failed to start phy timer\n"); > + } > + > if (!ad->is_safe_mode) { > ret =3D ice_flow_init(ad); > if (ret) { > @@ -5814,11 +5825,6 @@ ice_timesync_enable(struct rte_eth_dev *dev) > return -1; > } >=20 > - if (ice_is_e810(hw)) > - hw->phy_cfg =3D ICE_PHY_E810; > - else > - hw->phy_cfg =3D ICE_PHY_E822; > - > if (hw->func_caps.ts_func_info.src_tmr_owned) { > ret =3D ice_ptp_init_phc(hw); > if (ret) { > @@ -5939,16 +5945,17 @@ ice_timesync_read_time(struct rte_eth_dev > *dev, struct timespec *ts) > struct ice_hw *hw =3D ICE_DEV_PRIVATE_TO_HW(dev->data- > >dev_private); > struct ice_adapter *ad =3D > ICE_DEV_PRIVATE_TO_ADAPTER(dev->data- > >dev_private); > + uint8_t tmr_idx =3D hw->func_caps.ts_func_info.tmr_index_assoc; > uint32_t hi, lo, lo2; > uint64_t time, ns; >=20 > - lo =3D ICE_READ_REG(hw, GLTSYN_TIME_L(0)); > - hi =3D ICE_READ_REG(hw, GLTSYN_TIME_H(0)); > - lo2 =3D ICE_READ_REG(hw, GLTSYN_TIME_L(0)); > + lo =3D ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); > + hi =3D ICE_READ_REG(hw, GLTSYN_TIME_H(tmr_idx)); > + lo2 =3D ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); >=20 > if (lo2 < lo) { > - lo =3D ICE_READ_REG(hw, GLTSYN_TIME_L(0)); > - hi =3D ICE_READ_REG(hw, GLTSYN_TIME_H(0)); > + lo =3D ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); > + hi =3D ICE_READ_REG(hw, GLTSYN_TIME_H(tmr_idx)); > } >=20 > time =3D ((uint64_t)hi << 32) | lo; > @@ -5964,6 +5971,7 @@ ice_timesync_disable(struct rte_eth_dev *dev) > struct ice_hw *hw =3D ICE_DEV_PRIVATE_TO_HW(dev->data- > >dev_private); > struct ice_adapter *ad =3D > ICE_DEV_PRIVATE_TO_ADAPTER(dev->data- > >dev_private); > + uint8_t tmr_idx =3D hw->func_caps.ts_func_info.tmr_index_assoc; > uint64_t val; > uint8_t lport; >=20 > @@ -5971,12 +5979,12 @@ ice_timesync_disable(struct rte_eth_dev *dev) >=20 > ice_clear_phy_tstamp(hw, lport, 0); >=20 > - val =3D ICE_READ_REG(hw, GLTSYN_ENA(0)); > + val =3D ICE_READ_REG(hw, GLTSYN_ENA(tmr_idx)); > val &=3D ~GLTSYN_ENA_TSYN_ENA_M; > - ICE_WRITE_REG(hw, GLTSYN_ENA(0), val); > + ICE_WRITE_REG(hw, GLTSYN_ENA(tmr_idx), val); >=20 > - ICE_WRITE_REG(hw, GLTSYN_INCVAL_L(0), 0); > - ICE_WRITE_REG(hw, GLTSYN_INCVAL_H(0), 0); > + ICE_WRITE_REG(hw, GLTSYN_INCVAL_L(tmr_idx), 0); > + ICE_WRITE_REG(hw, GLTSYN_INCVAL_H(tmr_idx), 0); >=20 > ad->ptp_ena =3D 0; >=20 > diff --git a/drivers/net/ice/ice_rxtx.h b/drivers/net/ice/ice_rxtx.h inde= x > 4947d5c..94f6bcf 100644 > --- a/drivers/net/ice/ice_rxtx.h > +++ b/drivers/net/ice/ice_rxtx.h > @@ -349,26 +349,27 @@ static inline > uint64_t ice_tstamp_convert_32b_64b(struct ice_hw *hw, struct ice_adapte= r > *ad, > uint32_t flag, uint32_t in_timestamp) { > + uint8_t tmr_idx =3D hw->func_caps.ts_func_info.tmr_index_assoc; > const uint64_t mask =3D 0xFFFFFFFF; > uint32_t hi, lo, lo2, delta; > uint64_t ns; >=20 > if (flag) { > - lo =3D ICE_READ_REG(hw, GLTSYN_TIME_L(0)); > - hi =3D ICE_READ_REG(hw, GLTSYN_TIME_H(0)); > + lo =3D ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); > + hi =3D ICE_READ_REG(hw, GLTSYN_TIME_H(tmr_idx)); >=20 > /* > * On typical system, the delta between lo and lo2 is ~1000ns, > * so 10000 seems a large-enough but not overly-big guard > band. > */ > if (lo > (UINT32_MAX - > ICE_TIMESYNC_REG_WRAP_GUARD_BAND)) > - lo2 =3D ICE_READ_REG(hw, GLTSYN_TIME_L(0)); > + lo2 =3D ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); > else > lo2 =3D lo; >=20 > if (lo2 < lo) { > - lo =3D ICE_READ_REG(hw, GLTSYN_TIME_L(0)); > - hi =3D ICE_READ_REG(hw, GLTSYN_TIME_H(0)); > + lo =3D ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); > + hi =3D ICE_READ_REG(hw, GLTSYN_TIME_H(tmr_idx)); > } >=20 > ad->time_hw =3D ((uint64_t)hi << 32) | lo; > -- > 2.9.5 Acked-by: Wenjun Wu Regards, Wenjun